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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/vfsub-bf.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

404 lines
15 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
define <vscale x 1 x bfloat> @intrinsic_vfsub_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vv_nxv1bf16_nxv1bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.nxv1bf16(
<vscale x 1 x bfloat> poison,
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %1,
iXLen 7, iXLen %2)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfsub_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x bfloat> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv1bf16_nxv1bf16_nxv1bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu
; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.mask.nxv1bf16.nxv1bf16(
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %1,
<vscale x 1 x bfloat> %2,
<vscale x 1 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vfsub_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vv_nxv2bf16_nxv2bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.nxv2bf16(
<vscale x 2 x bfloat> poison,
<vscale x 2 x bfloat> %0,
<vscale x 2 x bfloat> %1,
iXLen 7, iXLen %2)
ret <vscale x 2 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vfsub_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x bfloat> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv2bf16_nxv2bf16_nxv2bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu
; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.mask.nxv2bf16.nxv2bf16(
<vscale x 2 x bfloat> %0,
<vscale x 2 x bfloat> %1,
<vscale x 2 x bfloat> %2,
<vscale x 2 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 2 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vfsub_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vv_nxv4bf16_nxv4bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.nxv4bf16(
<vscale x 4 x bfloat> poison,
<vscale x 4 x bfloat> %0,
<vscale x 4 x bfloat> %1,
iXLen 7, iXLen %2)
ret <vscale x 4 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vfsub_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x bfloat> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv4bf16_nxv4bf16_nxv4bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu
; CHECK-NEXT: vfsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.mask.nxv4bf16.nxv4bf16(
<vscale x 4 x bfloat> %0,
<vscale x 4 x bfloat> %1,
<vscale x 4 x bfloat> %2,
<vscale x 4 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 4 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vfsub_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vv_nxv8bf16_nxv8bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.nxv8bf16(
<vscale x 8 x bfloat> poison,
<vscale x 8 x bfloat> %0,
<vscale x 8 x bfloat> %1,
iXLen 7, iXLen %2)
ret <vscale x 8 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vfsub_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x bfloat> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv8bf16_nxv8bf16_nxv8bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu
; CHECK-NEXT: vfsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.mask.nxv8bf16.nxv8bf16(
<vscale x 8 x bfloat> %0,
<vscale x 8 x bfloat> %1,
<vscale x 8 x bfloat> %2,
<vscale x 8 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 8 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vfsub_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vv_nxv16bf16_nxv16bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.nxv16bf16(
<vscale x 16 x bfloat> poison,
<vscale x 16 x bfloat> %0,
<vscale x 16 x bfloat> %1,
iXLen 7, iXLen %2)
ret <vscale x 16 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vfsub_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x bfloat> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv16bf16_nxv16bf16_nxv16bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu
; CHECK-NEXT: vfsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.mask.nxv16bf16.nxv16bf16(
<vscale x 16 x bfloat> %0,
<vscale x 16 x bfloat> %1,
<vscale x 16 x bfloat> %2,
<vscale x 16 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 16 x bfloat> %a
}
define <vscale x 32 x bfloat> @intrinsic_vfsub_vv_nxv32bf16_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vv_nxv32bf16_nxv32bf16_nxv32bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
; CHECK-NEXT: vfsub.vv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vfsub.nxv32bf16.nxv32bf16(
<vscale x 32 x bfloat> poison,
<vscale x 32 x bfloat> %0,
<vscale x 32 x bfloat> %1,
iXLen 7, iXLen %2)
ret <vscale x 32 x bfloat> %a
}
define <vscale x 32 x bfloat> @intrinsic_vfsub_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x bfloat> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vv_nxv32bf16_nxv32bf16_nxv32bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16alt, m8, ta, mu
; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vfsub.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vfsub.mask.nxv32bf16.nxv32bf16(
<vscale x 32 x bfloat> %0,
<vscale x 32 x bfloat> %1,
<vscale x 32 x bfloat> %2,
<vscale x 32 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 32 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfsub_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, bfloat %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vf_nxv1bf16_nxv1bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.nxv1bf16.bf16(
<vscale x 1 x bfloat> poison,
<vscale x 1 x bfloat> %0,
bfloat %1,
iXLen 7, iXLen %2)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 1 x bfloat> @intrinsic_vfsub_mask_vf_nxv1bf16_nxv1bf16_bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, bfloat %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv1bf16_nxv1bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf4, ta, mu
; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfsub.mask.nxv1bf16.bf16(
<vscale x 1 x bfloat> %0,
<vscale x 1 x bfloat> %1,
bfloat %2,
<vscale x 1 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 1 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vfsub_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, bfloat %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vf_nxv2bf16_nxv2bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, ma
; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.nxv2bf16.bf16(
<vscale x 2 x bfloat> poison,
<vscale x 2 x bfloat> %0,
bfloat %1,
iXLen 7, iXLen %2)
ret <vscale x 2 x bfloat> %a
}
define <vscale x 2 x bfloat> @intrinsic_vfsub_mask_vf_nxv2bf16_nxv2bf16_bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, bfloat %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv2bf16_nxv2bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, mf2, ta, mu
; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x bfloat> @llvm.riscv.vfsub.mask.nxv2bf16.bf16(
<vscale x 2 x bfloat> %0,
<vscale x 2 x bfloat> %1,
bfloat %2,
<vscale x 2 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 2 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vfsub_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, bfloat %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vf_nxv4bf16_nxv4bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, ma
; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.nxv4bf16.bf16(
<vscale x 4 x bfloat> poison,
<vscale x 4 x bfloat> %0,
bfloat %1,
iXLen 7, iXLen %2)
ret <vscale x 4 x bfloat> %a
}
define <vscale x 4 x bfloat> @intrinsic_vfsub_mask_vf_nxv4bf16_nxv4bf16_bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, bfloat %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv4bf16_nxv4bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m1, ta, mu
; CHECK-NEXT: vfsub.vf v8, v9, fa0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfsub.mask.nxv4bf16.bf16(
<vscale x 4 x bfloat> %0,
<vscale x 4 x bfloat> %1,
bfloat %2,
<vscale x 4 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 4 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vfsub_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, bfloat %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vf_nxv8bf16_nxv8bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, ma
; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.nxv8bf16.bf16(
<vscale x 8 x bfloat> poison,
<vscale x 8 x bfloat> %0,
bfloat %1,
iXLen 7, iXLen %2)
ret <vscale x 8 x bfloat> %a
}
define <vscale x 8 x bfloat> @intrinsic_vfsub_mask_vf_nxv8bf16_nxv8bf16_bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, bfloat %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv8bf16_nxv8bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m2, ta, mu
; CHECK-NEXT: vfsub.vf v8, v10, fa0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfsub.mask.nxv8bf16.bf16(
<vscale x 8 x bfloat> %0,
<vscale x 8 x bfloat> %1,
bfloat %2,
<vscale x 8 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 8 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vfsub_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, bfloat %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vf_nxv16bf16_nxv16bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, ma
; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.nxv16bf16.bf16(
<vscale x 16 x bfloat> poison,
<vscale x 16 x bfloat> %0,
bfloat %1,
iXLen 7, iXLen %2)
ret <vscale x 16 x bfloat> %a
}
define <vscale x 16 x bfloat> @intrinsic_vfsub_mask_vf_nxv16bf16_nxv16bf16_bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, bfloat %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv16bf16_nxv16bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m4, ta, mu
; CHECK-NEXT: vfsub.vf v8, v12, fa0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfsub.mask.nxv16bf16.bf16(
<vscale x 16 x bfloat> %0,
<vscale x 16 x bfloat> %1,
bfloat %2,
<vscale x 16 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 16 x bfloat> %a
}
define <vscale x 32 x bfloat> @intrinsic_vfsub_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, bfloat %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vf_nxv32bf16_nxv32bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, ma
; CHECK-NEXT: vfsub.vf v8, v8, fa0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vfsub.nxv32bf16.bf16(
<vscale x 32 x bfloat> poison,
<vscale x 32 x bfloat> %0,
bfloat %1,
iXLen 7, iXLen %2)
ret <vscale x 32 x bfloat> %a
}
define <vscale x 32 x bfloat> @intrinsic_vfsub_mask_vf_nxv32bf16_nxv32bf16_bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, bfloat %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfsub_mask_vf_nxv32bf16_nxv32bf16_bf16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16alt, m8, ta, mu
; CHECK-NEXT: vfsub.vf v8, v16, fa0, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x bfloat> @llvm.riscv.vfsub.mask.nxv32bf16.bf16(
<vscale x 32 x bfloat> %0,
<vscale x 32 x bfloat> %1,
bfloat %2,
<vscale x 32 x i1> %3,
iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 32 x bfloat> %a
}
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