derek.holloway
7502bf64a4
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166 lines
6.1 KiB
LLVM
166 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfbfmin \
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; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfbfmin \
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; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
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define <vscale x 1 x float> @intrinsic_vfwcvtbf16_f.f.v_nxv1f32_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_f.f.v_nxv1f32_nxv1bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv1f32.nxv1bf16(
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<vscale x 1 x float> poison,
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<vscale x 1 x bfloat> %0,
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iXLen %1)
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ret <vscale x 1 x float> %a
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}
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define <vscale x 1 x float> @intrinsic_vfwcvtbf16_mask_f.f.v_nxv1f32_nxv1bf16(<vscale x 1 x float> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_mask_f.f.v_nxv1f32_nxv1bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9, v0.t
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv1f32.nxv1bf16(
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<vscale x 1 x float> %0,
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<vscale x 1 x bfloat> %1,
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<vscale x 1 x i1> %2,
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iXLen %3, iXLen 1)
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ret <vscale x 1 x float> %a
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}
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define <vscale x 2 x float> @intrinsic_vfwcvtbf16_f.f.v_nxv2f32_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_f.f.v_nxv2f32_nxv2bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv2f32.nxv2bf16(
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<vscale x 2 x float> poison,
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<vscale x 2 x bfloat> %0,
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iXLen %1)
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ret <vscale x 2 x float> %a
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}
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define <vscale x 2 x float> @intrinsic_vfwcvtbf16_mask_f.f.v_nxv2f32_nxv2bf16(<vscale x 2 x float> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_mask_f.f.v_nxv2f32_nxv2bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9, v0.t
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 2 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv2f32.nxv2bf16(
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<vscale x 2 x float> %0,
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<vscale x 2 x bfloat> %1,
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<vscale x 2 x i1> %2,
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iXLen %3, iXLen 1)
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ret <vscale x 2 x float> %a
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}
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define <vscale x 4 x float> @intrinsic_vfwcvtbf16_f.f.v_nxv4f32_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_f.f.v_nxv4f32_nxv4bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vmv1r.v v10, v8
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv4f32.nxv4bf16(
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<vscale x 4 x float> poison,
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<vscale x 4 x bfloat> %0,
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iXLen %1)
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ret <vscale x 4 x float> %a
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}
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define <vscale x 4 x float> @intrinsic_vfwcvtbf16_mask_f.f.v_nxv4f32_nxv4bf16(<vscale x 4 x float> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_mask_f.f.v_nxv4f32_nxv4bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v10, v0.t
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 4 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv4f32.nxv4bf16(
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<vscale x 4 x float> %0,
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<vscale x 4 x bfloat> %1,
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<vscale x 4 x i1> %2,
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iXLen %3, iXLen 1)
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ret <vscale x 4 x float> %a
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}
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define <vscale x 8 x float> @intrinsic_vfwcvtbf16_f.f.v_nxv8f32_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_f.f.v_nxv8f32_nxv8bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
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; CHECK-NEXT: vmv2r.v v12, v8
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v12
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv8f32.nxv8bf16(
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<vscale x 8 x float> poison,
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<vscale x 8 x bfloat> %0,
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iXLen %1)
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ret <vscale x 8 x float> %a
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}
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define <vscale x 8 x float> @intrinsic_vfwcvtbf16_mask_f.f.v_nxv8f32_nxv8bf16(<vscale x 8 x float> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_mask_f.f.v_nxv8f32_nxv8bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v12, v0.t
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 8 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv8f32.nxv8bf16(
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<vscale x 8 x float> %0,
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<vscale x 8 x bfloat> %1,
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<vscale x 8 x i1> %2,
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iXLen %3, iXLen 1)
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ret <vscale x 8 x float> %a
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}
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define <vscale x 16 x float> @intrinsic_vfwcvtbf16_f.f.v_nxv16f32_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_f.f.v_nxv16f32_nxv16bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
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; CHECK-NEXT: vmv4r.v v16, v8
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.nxv16f32.nxv16bf16(
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<vscale x 16 x float> poison,
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<vscale x 16 x bfloat> %0,
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iXLen %1)
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ret <vscale x 16 x float> %a
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}
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define <vscale x 16 x float> @intrinsic_vfwcvtbf16_mask_f.f.v_nxv16f32_nxv16bf16(<vscale x 16 x float> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwcvtbf16_mask_f.f.v_nxv16f32_nxv16bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
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; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v16, v0.t
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 16 x float> @llvm.riscv.vfwcvtbf16.f.f.v.mask.nxv16f32.nxv16bf16(
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<vscale x 16 x float> %0,
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<vscale x 16 x bfloat> %1,
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<vscale x 16 x i1> %2,
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iXLen %3, iXLen 1)
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ret <vscale x 16 x float> %a
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}
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