derek.holloway
7502bf64a4
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60 lines
2.2 KiB
LLVM
60 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
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; Check that EVL tail folded loops from the loop vectorizer are able to have the
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; vl of non-VP instructions reduced.
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define void @evl_tail_folded(ptr %p, ptr %q) {
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; CHECK-LABEL: evl_tail_folded:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: csrr a3, vlenb
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; CHECK-NEXT: srli a3, a3, 2
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; CHECK-NEXT: addi a4, a3, 1023
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; CHECK-NEXT: neg a5, a3
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; CHECK-NEXT: and a4, a4, a5
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; CHECK-NEXT: li a5, 1024
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; CHECK-NEXT: .LBB0_1: # %vector.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: sub a6, a5, a2
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; CHECK-NEXT: slli a7, a2, 3
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; CHECK-NEXT: vsetvli a6, a6, e64, m2, ta, ma
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; CHECK-NEXT: add t0, a0, a7
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; CHECK-NEXT: vle64.v v8, (t0)
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; CHECK-NEXT: sub a4, a4, a3
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; CHECK-NEXT: add a7, a1, a7
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; CHECK-NEXT: vadd.vi v8, v8, 1
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; CHECK-NEXT: vse64.v v8, (a7)
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; CHECK-NEXT: add a2, a2, a6
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; CHECK-NEXT: bnez a4, .LBB0_1
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; CHECK-NEXT: # %bb.2: # %exit
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.vscale.i64()
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%1 = shl i64 %0, 1
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%n.rnd.up = add i64 %1, 1023
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%n.mod.vf = urem i64 %n.rnd.up, %1
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%n.vec = sub i64 %n.rnd.up, %n.mod.vf
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%2 = tail call i64 @llvm.vscale.i64()
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%3 = shl i64 %2, 1
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%evl.based.iv = phi i64 [ 0, %entry ], [ %index.evl.next, %vector.body ]
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%avl = sub i64 1024, %evl.based.iv
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%4 = tail call i32 @llvm.experimental.get.vector.length.i64(i64 %avl, i32 2, i1 true)
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%5 = getelementptr i64, ptr %p, i64 %evl.based.iv
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%vp.op.load = tail call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr %5, <vscale x 2 x i1> splat (i1 true), i32 %4)
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%6 = add <vscale x 2 x i64> %vp.op.load, splat (i64 1)
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%7 = getelementptr i64, ptr %q, i64 %evl.based.iv
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tail call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> %6, ptr %7, <vscale x 2 x i1> splat (i1 true), i32 %4)
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%8 = zext i32 %4 to i64
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%index.evl.next = add i64 %evl.based.iv, %8
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%index.next = add i64 %index, %3
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%9 = icmp eq i64 %index.next, %n.vec
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br i1 %9, label %exit, label %vector.body
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exit:
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ret void
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}
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