derek.holloway
7502bf64a4
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284 lines
8.9 KiB
LLVM
284 lines
8.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
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define signext i8 @intrinsic_vmv.x.s_s_nxv1i8(<vscale x 1 x i8> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i8 @llvm.riscv.vmv.x.s.nxv1i8(<vscale x 1 x i8> %0)
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ret i8 %a
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}
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define signext i8 @intrinsic_vmv.x.s_s_nxv2i8(<vscale x 2 x i8> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i8 @llvm.riscv.vmv.x.s.nxv2i8(<vscale x 2 x i8> %0)
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ret i8 %a
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}
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define signext i8 @intrinsic_vmv.x.s_s_nxv4i8(<vscale x 4 x i8> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i8 @llvm.riscv.vmv.x.s.nxv4i8(<vscale x 4 x i8> %0)
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ret i8 %a
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}
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define signext i8 @intrinsic_vmv.x.s_s_nxv8i8(<vscale x 8 x i8> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i8 @llvm.riscv.vmv.x.s.nxv8i8(<vscale x 8 x i8> %0)
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ret i8 %a
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}
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define signext i8 @intrinsic_vmv.x.s_s_nxv16i8(<vscale x 16 x i8> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i8 @llvm.riscv.vmv.x.s.nxv16i8(<vscale x 16 x i8> %0)
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ret i8 %a
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}
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define signext i8 @intrinsic_vmv.x.s_s_nxv32i8(<vscale x 32 x i8> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv32i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i8 @llvm.riscv.vmv.x.s.nxv32i8(<vscale x 32 x i8> %0)
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ret i8 %a
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}
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define signext i8 @intrinsic_vmv.x.s_s_nxv64i8(<vscale x 64 x i8> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv64i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i8 @llvm.riscv.vmv.x.s.nxv64i8(<vscale x 64 x i8> %0)
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ret i8 %a
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}
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define signext i16 @intrinsic_vmv.x.s_s_nxv1i16(<vscale x 1 x i16> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i16 @llvm.riscv.vmv.x.s.nxv1i16(<vscale x 1 x i16> %0)
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ret i16 %a
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}
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define signext i16 @intrinsic_vmv.x.s_s_nxv2i16(<vscale x 2 x i16> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i16 @llvm.riscv.vmv.x.s.nxv2i16(<vscale x 2 x i16> %0)
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ret i16 %a
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}
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define signext i16 @intrinsic_vmv.x.s_s_nxv4i16(<vscale x 4 x i16> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i16 @llvm.riscv.vmv.x.s.nxv4i16(<vscale x 4 x i16> %0)
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ret i16 %a
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}
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define signext i16 @intrinsic_vmv.x.s_s_nxv8i16(<vscale x 8 x i16> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i16 @llvm.riscv.vmv.x.s.nxv8i16(<vscale x 8 x i16> %0)
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ret i16 %a
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}
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define signext i16 @intrinsic_vmv.x.s_s_nxv16i16(<vscale x 16 x i16> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i16 @llvm.riscv.vmv.x.s.nxv16i16( <vscale x 16 x i16> %0)
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ret i16 %a
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}
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define signext i16 @intrinsic_vmv.x.s_s_nxv32i16(<vscale x 32 x i16> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv32i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i16 @llvm.riscv.vmv.x.s.nxv32i16( <vscale x 32 x i16> %0)
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ret i16 %a
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}
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define signext i32 @intrinsic_vmv.x.s_s_nxv1i32(<vscale x 1 x i32> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv1i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i32 @llvm.riscv.vmv.x.s.nxv1i32( <vscale x 1 x i32> %0)
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ret i32 %a
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}
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define signext i32 @intrinsic_vmv.x.s_s_nxv2i32(<vscale x 2 x i32> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv2i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i32 @llvm.riscv.vmv.x.s.nxv2i32( <vscale x 2 x i32> %0)
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ret i32 %a
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}
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define signext i32 @intrinsic_vmv.x.s_s_nxv4i32(<vscale x 4 x i32> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv4i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i32 @llvm.riscv.vmv.x.s.nxv4i32( <vscale x 4 x i32> %0)
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ret i32 %a
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}
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define signext i32 @intrinsic_vmv.x.s_s_nxv8i32(<vscale x 8 x i32> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv8i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i32 @llvm.riscv.vmv.x.s.nxv8i32( <vscale x 8 x i32> %0)
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ret i32 %a
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}
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define signext i32 @intrinsic_vmv.x.s_s_nxv16i32(<vscale x 16 x i32> %0) nounwind {
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; CHECK-LABEL: intrinsic_vmv.x.s_s_nxv16i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%a = call i32 @llvm.riscv.vmv.x.s.nxv16i32( <vscale x 16 x i32> %0)
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ret i32 %a
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}
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define i64 @intrinsic_vmv.x.s_s_nxv1i64(<vscale x 1 x i64> %0) nounwind {
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; RV32-LABEL: intrinsic_vmv.x.s_s_nxv1i64:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a0, 32
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; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; RV32-NEXT: vsrl.vx v9, v8, a0
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; RV32-NEXT: vmv.x.s a1, v9
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; RV32-NEXT: vmv.x.s a0, v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: intrinsic_vmv.x.s_s_nxv1i64:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; RV64-NEXT: vmv.x.s a0, v8
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; RV64-NEXT: ret
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entry:
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%a = call i64 @llvm.riscv.vmv.x.s.nxv1i64( <vscale x 1 x i64> %0)
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ret i64 %a
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}
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define i64 @intrinsic_vmv.x.s_s_nxv2i64(<vscale x 2 x i64> %0) nounwind {
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; RV32-LABEL: intrinsic_vmv.x.s_s_nxv2i64:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a0, 32
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; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma
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; RV32-NEXT: vsrl.vx v10, v8, a0
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; RV32-NEXT: vmv.x.s a1, v10
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; RV32-NEXT: vmv.x.s a0, v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: intrinsic_vmv.x.s_s_nxv2i64:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; RV64-NEXT: vmv.x.s a0, v8
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; RV64-NEXT: ret
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entry:
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%a = call i64 @llvm.riscv.vmv.x.s.nxv2i64( <vscale x 2 x i64> %0)
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ret i64 %a
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}
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define i64 @intrinsic_vmv.x.s_s_nxv4i64(<vscale x 4 x i64> %0) nounwind {
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; RV32-LABEL: intrinsic_vmv.x.s_s_nxv4i64:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a0, 32
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; RV32-NEXT: vsetivli zero, 1, e64, m4, ta, ma
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; RV32-NEXT: vsrl.vx v12, v8, a0
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; RV32-NEXT: vmv.x.s a1, v12
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; RV32-NEXT: vmv.x.s a0, v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: intrinsic_vmv.x.s_s_nxv4i64:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; RV64-NEXT: vmv.x.s a0, v8
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; RV64-NEXT: ret
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entry:
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%a = call i64 @llvm.riscv.vmv.x.s.nxv4i64( <vscale x 4 x i64> %0)
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ret i64 %a
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}
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define i64 @intrinsic_vmv.x.s_s_nxv8i64(<vscale x 8 x i64> %0) nounwind {
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; RV32-LABEL: intrinsic_vmv.x.s_s_nxv8i64:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a0, 32
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; RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma
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; RV32-NEXT: vsrl.vx v16, v8, a0
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; RV32-NEXT: vmv.x.s a1, v16
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; RV32-NEXT: vmv.x.s a0, v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: intrinsic_vmv.x.s_s_nxv8i64:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
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; RV64-NEXT: vmv.x.s a0, v8
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; RV64-NEXT: ret
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entry:
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%a = call i64 @llvm.riscv.vmv.x.s.nxv8i64(<vscale x 8 x i64> %0)
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ret i64 %a
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}
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