derek.holloway
7502bf64a4
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372 lines
15 KiB
LLVM
372 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x i1> @test_vp_reverse_nxv1i1_masked(<vscale x 1 x i1> %src, <vscale x 1 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv1i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v10, v0.t
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; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
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; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
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; CHECK-NEXT: ret
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%dst = call <vscale x 1 x i1> @llvm.experimental.vp.reverse.nxv1i1(<vscale x 1 x i1> %src, <vscale x 1 x i1> %mask, i32 %evl)
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ret <vscale x 1 x i1> %dst
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}
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define <vscale x 1 x i1> @test_vp_reverse_nxv1i1(<vscale x 1 x i1> %src, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, a0, -1
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vrsub.vx v8, v8, a1
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vrgatherei16.vv v10, v9, v8
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: ret
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%dst = call <vscale x 1 x i1> @llvm.experimental.vp.reverse.nxv1i1(<vscale x 1 x i1> %src, <vscale x 1 x i1> splat (i1 1), i32 %evl)
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ret <vscale x 1 x i1> %dst
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}
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define <vscale x 2 x i1> @test_vp_reverse_nxv2i1_masked(<vscale x 2 x i1> %src, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv2i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vid.v v10, v0.t
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; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
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; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
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; CHECK-NEXT: ret
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%dst = call <vscale x 2 x i1> @llvm.experimental.vp.reverse.nxv2i1(<vscale x 2 x i1> %src, <vscale x 2 x i1> %mask, i32 %evl)
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ret <vscale x 2 x i1> %dst
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}
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define <vscale x 2 x i1> @test_vp_reverse_nxv2i1(<vscale x 2 x i1> %src, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, a0, -1
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vrsub.vx v8, v8, a1
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; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vrgatherei16.vv v10, v9, v8
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: ret
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%dst = call <vscale x 2 x i1> @llvm.experimental.vp.reverse.nxv2i1(<vscale x 2 x i1> %src, <vscale x 2 x i1> splat (i1 1), i32 %evl)
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ret <vscale x 2 x i1> %dst
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}
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define <vscale x 4 x i1> @test_vp_reverse_nxv4i1_masked(<vscale x 4 x i1> %src, <vscale x 4 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv4i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; CHECK-NEXT: vid.v v10, v0.t
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; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v11, v9, v10, v0.t
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; CHECK-NEXT: vmsne.vi v0, v11, 0, v0.t
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; CHECK-NEXT: ret
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%dst = call <vscale x 4 x i1> @llvm.experimental.vp.reverse.nxv4i1(<vscale x 4 x i1> %src, <vscale x 4 x i1> %mask, i32 %evl)
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ret <vscale x 4 x i1> %dst
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}
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define <vscale x 4 x i1> @test_vp_reverse_nxv4i1(<vscale x 4 x i1> %src, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, a0, -1
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; CHECK-NEXT: vrsub.vx v8, v8, a1
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; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vrgatherei16.vv v10, v9, v8
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; CHECK-NEXT: vmsne.vi v0, v10, 0
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; CHECK-NEXT: ret
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%dst = call <vscale x 4 x i1> @llvm.experimental.vp.reverse.nxv4i1(<vscale x 4 x i1> %src, <vscale x 4 x i1> splat (i1 1), i32 %evl)
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ret <vscale x 4 x i1> %dst
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}
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define <vscale x 8 x i1> @test_vp_reverse_nxv8i1_masked(<vscale x 8 x i1> %src, <vscale x 8 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv8i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v9, 0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vid.v v10, v0.t
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; CHECK-NEXT: vrsub.vx v10, v10, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v12, v9, v10, v0.t
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; CHECK-NEXT: vmsne.vi v0, v12, 0, v0.t
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; CHECK-NEXT: ret
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%dst = call <vscale x 8 x i1> @llvm.experimental.vp.reverse.nxv8i1(<vscale x 8 x i1> %src, <vscale x 8 x i1> %mask, i32 %evl)
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ret <vscale x 8 x i1> %dst
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}
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define <vscale x 8 x i1> @test_vp_reverse_nxv8i1(<vscale x 8 x i1> %src, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, a0, -1
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; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vx v8, v8, a1
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vrgatherei16.vv v11, v10, v8
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; CHECK-NEXT: vmsne.vi v0, v11, 0
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; CHECK-NEXT: ret
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%dst = call <vscale x 8 x i1> @llvm.experimental.vp.reverse.nxv8i1(<vscale x 8 x i1> %src, <vscale x 8 x i1> splat (i1 1), i32 %evl)
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ret <vscale x 8 x i1> %dst
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}
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define <vscale x 16 x i1> @test_vp_reverse_nxv16i1_masked(<vscale x 16 x i1> %src, <vscale x 16 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv16i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vmerge.vim v10, v10, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vid.v v12, v0.t
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; CHECK-NEXT: vrsub.vx v12, v12, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v16, v10, v12, v0.t
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; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: ret
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%dst = call <vscale x 16 x i1> @llvm.experimental.vp.reverse.nxv16i1(<vscale x 16 x i1> %src, <vscale x 16 x i1> %mask, i32 %evl)
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ret <vscale x 16 x i1> %dst
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}
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define <vscale x 16 x i1> @test_vp_reverse_nxv16i1(<vscale x 16 x i1> %src, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, a0, -1
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; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v12, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vrsub.vx v8, v8, a1
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
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; CHECK-NEXT: vrgatherei16.vv v14, v12, v8
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; CHECK-NEXT: vmsne.vi v0, v14, 0
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; CHECK-NEXT: ret
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%dst = call <vscale x 16 x i1> @llvm.experimental.vp.reverse.nxv16i1(<vscale x 16 x i1> %src, <vscale x 16 x i1> splat (i1 1), i32 %evl)
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ret <vscale x 16 x i1> %dst
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}
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define <vscale x 32 x i1> @test_vp_reverse_nxv32i1_masked(<vscale x 32 x i1> %src, <vscale x 32 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv32i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
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; CHECK-NEXT: vmv.v.i v12, 0
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vmerge.vim v12, v12, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
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; CHECK-NEXT: vid.v v16, v0.t
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; CHECK-NEXT: vrsub.vx v16, v16, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v24, v12, v16, v0.t
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; CHECK-NEXT: vmsne.vi v8, v24, 0, v0.t
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: ret
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%dst = call <vscale x 32 x i1> @llvm.experimental.vp.reverse.nxv32i1(<vscale x 32 x i1> %src, <vscale x 32 x i1> %mask, i32 %evl)
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ret <vscale x 32 x i1> %dst
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}
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define <vscale x 32 x i1> @test_vp_reverse_nxv32i1(<vscale x 32 x i1> %src, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv32i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, a0, -1
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; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
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; CHECK-NEXT: vmv.v.i v16, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, m8, ta, ma
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; CHECK-NEXT: vrsub.vx v8, v8, a1
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; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
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; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
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; CHECK-NEXT: vrgatherei16.vv v20, v16, v8
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; CHECK-NEXT: vmsne.vi v0, v20, 0
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; CHECK-NEXT: ret
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%dst = call <vscale x 32 x i1> @llvm.experimental.vp.reverse.nxv32i1(<vscale x 32 x i1> %src, <vscale x 32 x i1> splat (i1 1), i32 %evl)
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ret <vscale x 32 x i1> %dst
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}
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define <vscale x 64 x i1> @test_vp_reverse_nxv64i1_masked(<vscale x 64 x i1> %src, <vscale x 64 x i1> %mask, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv64i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v16, 0
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma
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; CHECK-NEXT: vid.v v10
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; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
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; CHECK-NEXT: addi a2, a1, -1
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vx v10, v10, a2
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v31, v16, v10
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; CHECK-NEXT: vrgatherei16.vv v30, v17, v10
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; CHECK-NEXT: vrgatherei16.vv v29, v18, v10
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; CHECK-NEXT: vrgatherei16.vv v28, v19, v10
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; CHECK-NEXT: vrgatherei16.vv v27, v20, v10
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; CHECK-NEXT: vrgatherei16.vv v26, v21, v10
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; CHECK-NEXT: vrgatherei16.vv v25, v22, v10
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; CHECK-NEXT: vrgatherei16.vv v24, v23, v10
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; CHECK-NEXT: sub a1, a1, a0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vslidedown.vx v16, v24, a1, v0.t
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; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: ret
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%dst = call <vscale x 64 x i1> @llvm.experimental.vp.reverse.nxv64i1(<vscale x 64 x i1> %src, <vscale x 64 x i1> %mask, i32 %evl)
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ret <vscale x 64 x i1> %dst
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}
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define <vscale x 64 x i1> @test_vp_reverse_nxv64i1(<vscale x 64 x i1> %src, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv64i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 0
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma
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; CHECK-NEXT: vid.v v16
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; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
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; CHECK-NEXT: addi a2, a1, -1
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vx v24, v16, a2
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v23, v8, v24
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; CHECK-NEXT: vrgatherei16.vv v22, v9, v24
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; CHECK-NEXT: vrgatherei16.vv v21, v10, v24
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; CHECK-NEXT: vrgatherei16.vv v20, v11, v24
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; CHECK-NEXT: vrgatherei16.vv v19, v12, v24
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; CHECK-NEXT: vrgatherei16.vv v18, v13, v24
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; CHECK-NEXT: vrgatherei16.vv v17, v14, v24
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; CHECK-NEXT: vrgatherei16.vv v16, v15, v24
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; CHECK-NEXT: sub a1, a1, a0
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; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
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; CHECK-NEXT: vslidedown.vx v8, v16, a1
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%dst = call <vscale x 64 x i1> @llvm.experimental.vp.reverse.nxv64i1(<vscale x 64 x i1> %src, <vscale x 64 x i1> splat (i1 1), i32 %evl)
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ret <vscale x 64 x i1> %dst
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}
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; nxv128i1 is split via the generic SplitVecRes_VP_REVERSE stack round-trip.
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; The i1 elements must be widened to a byte type so the strided store uses a
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; per-element stride, not stride 0 (which aliases every lane to one slot).
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define <vscale x 128 x i1> @test_vp_reverse_nxv128i1(<vscale x 128 x i1> %src, i32 zeroext %evl) {
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; CHECK-LABEL: test_vp_reverse_nxv128i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v16, 0
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; CHECK-NEXT: csrr a2, vlenb
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|
; CHECK-NEXT: slli a2, a2, 3
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|
; CHECK-NEXT: vmerge.vim v24, v16, 1, v0
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|
; CHECK-NEXT: mv a1, a0
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|
; CHECK-NEXT: bltu a0, a2, .LBB14_2
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; CHECK-NEXT: # %bb.1:
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|
; CHECK-NEXT: mv a1, a2
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|
; CHECK-NEXT: .LBB14_2:
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|
; CHECK-NEXT: addi sp, sp, -80
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|
; CHECK-NEXT: .cfi_def_cfa_offset 80
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|
; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
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|
; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
|
|
; CHECK-NEXT: .cfi_offset ra, -8
|
|
; CHECK-NEXT: .cfi_offset s0, -16
|
|
; CHECK-NEXT: addi s0, sp, 80
|
|
; CHECK-NEXT: .cfi_def_cfa s0, 0
|
|
; CHECK-NEXT: csrr a3, vlenb
|
|
; CHECK-NEXT: slli a3, a3, 4
|
|
; CHECK-NEXT: sub sp, sp, a3
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|
; CHECK-NEXT: andi sp, sp, -64
|
|
; CHECK-NEXT: vmv1r.v v0, v8
|
|
; CHECK-NEXT: addi a3, sp, 64
|
|
; CHECK-NEXT: li a4, -1
|
|
; CHECK-NEXT: sub a5, a0, a2
|
|
; CHECK-NEXT: add a6, a0, a3
|
|
; CHECK-NEXT: sltu a0, a0, a5
|
|
; CHECK-NEXT: add a2, a3, a2
|
|
; CHECK-NEXT: addi a6, a6, -1
|
|
; CHECK-NEXT: addi a0, a0, -1
|
|
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
|
|
; CHECK-NEXT: vsse8.v v24, (a6), a4
|
|
; CHECK-NEXT: sub a6, a6, a1
|
|
; CHECK-NEXT: and a0, a0, a5
|
|
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmerge.vim v8, v16, 1, v0
|
|
; CHECK-NEXT: vsse8.v v8, (a6), a4
|
|
; CHECK-NEXT: vle8.v v8, (a2)
|
|
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
|
|
; CHECK-NEXT: vle8.v v16, (a3)
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vand.vi v24, v8, 1
|
|
; CHECK-NEXT: vand.vi v16, v16, 1
|
|
; CHECK-NEXT: vmsne.vi v8, v24, 0
|
|
; CHECK-NEXT: vmsne.vi v0, v16, 0
|
|
; CHECK-NEXT: addi sp, s0, -80
|
|
; CHECK-NEXT: .cfi_def_cfa sp, 80
|
|
; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
|
|
; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
|
|
; CHECK-NEXT: .cfi_restore ra
|
|
; CHECK-NEXT: .cfi_restore s0
|
|
; CHECK-NEXT: addi sp, sp, 80
|
|
; CHECK-NEXT: .cfi_def_cfa_offset 0
|
|
; CHECK-NEXT: ret
|
|
%dst = call <vscale x 128 x i1> @llvm.experimental.vp.reverse.nxv128i1(<vscale x 128 x i1> %src, <vscale x 128 x i1> splat (i1 1), i32 %evl)
|
|
ret <vscale x 128 x i1> %dst
|
|
}
|
|
|