derek.holloway
7502bf64a4
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166 lines
8.5 KiB
LLVM
166 lines
8.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+m,+zfbfmin,+zvfbfmin -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+m,+zfbfmin,+zvfbfmin -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+d,+v,+zvfh,+m,+zfbfmin,+zvfbfmin -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+v,+zvfh,+m,+zfbfmin,+zvfbfmin -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x bfloat> @vpmerge_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vv_nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
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; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x bfloat> @llvm.vp.merge.nxv1bf16(<vscale x 1 x i1> %m, <vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, i32 %evl)
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ret <vscale x 1 x bfloat> %v
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}
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define <vscale x 1 x bfloat> @vpmerge_vf_nxv1bf16(bfloat %a, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vf_nxv1bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.x.h a1, fa0
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a1
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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%elt.head = insertelement <vscale x 1 x bfloat> poison, bfloat %a, i32 0
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%va = shufflevector <vscale x 1 x bfloat> %elt.head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
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%v = call <vscale x 1 x bfloat> @llvm.vp.merge.nxv1bf16(<vscale x 1 x i1> %m, <vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, i32 %evl)
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ret <vscale x 1 x bfloat> %v
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}
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define <vscale x 2 x bfloat> @vpmerge_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vv_nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
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; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x bfloat> @llvm.vp.merge.nxv2bf16(<vscale x 2 x i1> %m, <vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 %evl)
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ret <vscale x 2 x bfloat> %v
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}
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define <vscale x 2 x bfloat> @vpmerge_vf_nxv2bf16(bfloat %a, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vf_nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.x.h a1, fa0
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a1
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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%elt.head = insertelement <vscale x 2 x bfloat> poison, bfloat %a, i32 0
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%va = shufflevector <vscale x 2 x bfloat> %elt.head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
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%v = call <vscale x 2 x bfloat> @llvm.vp.merge.nxv2bf16(<vscale x 2 x i1> %m, <vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 %evl)
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ret <vscale x 2 x bfloat> %v
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}
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define <vscale x 4 x bfloat> @vpmerge_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vv_nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
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; CHECK-NEXT: vmerge.vvm v9, v9, v8, v0
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; CHECK-NEXT: vmv1r.v v8, v9
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x bfloat> @llvm.vp.merge.nxv4bf16(<vscale x 4 x i1> %m, <vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, i32 %evl)
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ret <vscale x 4 x bfloat> %v
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}
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define <vscale x 4 x bfloat> @vpmerge_vf_nxv4bf16(bfloat %a, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vf_nxv4bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.x.h a1, fa0
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a1
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
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; CHECK-NEXT: ret
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%elt.head = insertelement <vscale x 4 x bfloat> poison, bfloat %a, i32 0
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%va = shufflevector <vscale x 4 x bfloat> %elt.head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
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%v = call <vscale x 4 x bfloat> @llvm.vp.merge.nxv4bf16(<vscale x 4 x i1> %m, <vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, i32 %evl)
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ret <vscale x 4 x bfloat> %v
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}
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define <vscale x 8 x bfloat> @vpmerge_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vv_nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
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; CHECK-NEXT: vmerge.vvm v10, v10, v8, v0
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x bfloat> @llvm.vp.merge.nxv8bf16(<vscale x 8 x i1> %m, <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, i32 %evl)
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ret <vscale x 8 x bfloat> %v
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}
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define <vscale x 8 x bfloat> @vpmerge_vf_nxv8bf16(bfloat %a, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vf_nxv8bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.x.h a1, fa0
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; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a1
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
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; CHECK-NEXT: ret
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%elt.head = insertelement <vscale x 8 x bfloat> poison, bfloat %a, i32 0
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%va = shufflevector <vscale x 8 x bfloat> %elt.head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
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%v = call <vscale x 8 x bfloat> @llvm.vp.merge.nxv8bf16(<vscale x 8 x i1> %m, <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, i32 %evl)
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ret <vscale x 8 x bfloat> %v
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}
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define <vscale x 16 x bfloat> @vpmerge_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vv_nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
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; CHECK-NEXT: vmerge.vvm v12, v12, v8, v0
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; CHECK-NEXT: vmv4r.v v8, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x bfloat> @llvm.vp.merge.nxv16bf16(<vscale x 16 x i1> %m, <vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, i32 %evl)
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ret <vscale x 16 x bfloat> %v
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}
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define <vscale x 16 x bfloat> @vpmerge_vf_nxv16bf16(bfloat %a, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vf_nxv16bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.x.h a1, fa0
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; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a1
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
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; CHECK-NEXT: ret
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%elt.head = insertelement <vscale x 16 x bfloat> poison, bfloat %a, i32 0
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%va = shufflevector <vscale x 16 x bfloat> %elt.head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer
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%v = call <vscale x 16 x bfloat> @llvm.vp.merge.nxv16bf16(<vscale x 16 x i1> %m, <vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, i32 %evl)
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ret <vscale x 16 x bfloat> %v
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}
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define <vscale x 32 x bfloat> @vpmerge_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vv_nxv32bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
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; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
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; CHECK-NEXT: vmv8r.v v8, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x bfloat> @llvm.vp.merge.nxv32bf16(<vscale x 32 x i1> %m, <vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, i32 %evl)
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ret <vscale x 32 x bfloat> %v
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}
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define <vscale x 32 x bfloat> @vpmerge_vf_nxv32bf16(bfloat %a, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpmerge_vf_nxv32bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmv.x.h a1, fa0
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; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
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; CHECK-NEXT: vmv.v.x v16, a1
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; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, ma
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; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
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; CHECK-NEXT: ret
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%elt.head = insertelement <vscale x 32 x bfloat> poison, bfloat %a, i32 0
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%va = shufflevector <vscale x 32 x bfloat> %elt.head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer
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%v = call <vscale x 32 x bfloat> @llvm.vp.merge.nxv32bf16(<vscale x 32 x i1> %m, <vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, i32 %evl)
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ret <vscale x 32 x bfloat> %v
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}
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