derek.holloway
7502bf64a4
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272 lines
11 KiB
LLVM
272 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFHMIN
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define half @vpreduce_fmin_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fmin_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vfredmin.vs v9, v8, v9, v0.t
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; ZVFH-NEXT: vfmv.f.s fa0, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vpreduce_fmin_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
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; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v8, v0.t
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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%s = call half @llvm.vp.reduce.fmin.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret half %s
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}
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define half @vpreduce_fmax_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fmax_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vfredmax.vs v9, v8, v9, v0.t
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; ZVFH-NEXT: vfmv.f.s fa0, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vpreduce_fmax_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
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; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v8, v0.t
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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%s = call half @llvm.vp.reduce.fmax.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret half %s
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}
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define half @vpreduce_fmin_nnan_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fmin_nnan_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vfredmin.vs v9, v8, v9, v0.t
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; ZVFH-NEXT: vfmv.f.s fa0, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vpreduce_fmin_nnan_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
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; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v8, v0.t
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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%s = call nnan half @llvm.vp.reduce.fmin.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret half %s
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}
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define half @vpreduce_fmax_nnan_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fmax_nnan_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vfredmax.vs v9, v8, v9, v0.t
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; ZVFH-NEXT: vfmv.f.s fa0, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vpreduce_fmax_nnan_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
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; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v8, v0.t
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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%s = call nnan half @llvm.vp.reduce.fmax.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret half %s
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}
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define half @vpreduce_fminimum_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fminimum_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vmfne.vv v9, v8, v8, v0.t
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; ZVFH-NEXT: fcvt.s.h fa5, fa0
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; ZVFH-NEXT: vcpop.m a1, v9, v0.t
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; ZVFH-NEXT: feq.s a2, fa5, fa5
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; ZVFH-NEXT: xori a2, a2, 1
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; ZVFH-NEXT: or a1, a1, a2
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; ZVFH-NEXT: beqz a1, .LBB4_2
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; ZVFH-NEXT: # %bb.1:
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; ZVFH-NEXT: lui a0, 8
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; ZVFH-NEXT: addi a0, a0, -512
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; ZVFH-NEXT: fmv.h.x fa0, a0
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; ZVFH-NEXT: ret
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; ZVFH-NEXT: .LBB4_2:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vfredmin.vs v9, v8, v9, v0.t
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; ZVFH-NEXT: vfmv.f.s fa0, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vpreduce_fminimum_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t
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; ZVFHMIN-NEXT: feq.s a1, fa5, fa5
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; ZVFHMIN-NEXT: vcpop.m a2, v8, v0.t
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; ZVFHMIN-NEXT: xori a1, a1, 1
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; ZVFHMIN-NEXT: or a1, a2, a1
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; ZVFHMIN-NEXT: beqz a1, .LBB4_2
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; ZVFHMIN-NEXT: # %bb.1:
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; ZVFHMIN-NEXT: lui a0, 523264
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; ZVFHMIN-NEXT: fmv.w.x fa5, a0
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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; ZVFHMIN-NEXT: .LBB4_2:
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; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
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; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v8, v0.t
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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%s = call half @llvm.vp.reduce.fminimum.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret half %s
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}
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define half @vpreduce_fmaximum_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fmaximum_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vmfne.vv v9, v8, v8, v0.t
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; ZVFH-NEXT: fcvt.s.h fa5, fa0
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; ZVFH-NEXT: vcpop.m a1, v9, v0.t
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; ZVFH-NEXT: feq.s a2, fa5, fa5
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; ZVFH-NEXT: xori a2, a2, 1
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; ZVFH-NEXT: or a1, a1, a2
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; ZVFH-NEXT: beqz a1, .LBB5_2
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; ZVFH-NEXT: # %bb.1:
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; ZVFH-NEXT: lui a0, 8
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; ZVFH-NEXT: addi a0, a0, -512
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; ZVFH-NEXT: fmv.h.x fa0, a0
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; ZVFH-NEXT: ret
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; ZVFH-NEXT: .LBB5_2:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vfredmax.vs v9, v8, v9, v0.t
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; ZVFH-NEXT: vfmv.f.s fa0, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vpreduce_fmaximum_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t
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; ZVFHMIN-NEXT: feq.s a1, fa5, fa5
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; ZVFHMIN-NEXT: vcpop.m a2, v8, v0.t
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; ZVFHMIN-NEXT: xori a1, a1, 1
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; ZVFHMIN-NEXT: or a1, a2, a1
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; ZVFHMIN-NEXT: beqz a1, .LBB5_2
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; ZVFHMIN-NEXT: # %bb.1:
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; ZVFHMIN-NEXT: lui a0, 523264
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; ZVFHMIN-NEXT: fmv.w.x fa5, a0
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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; ZVFHMIN-NEXT: .LBB5_2:
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; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
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; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v8, v0.t
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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%s = call half @llvm.vp.reduce.fmaximum.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret half %s
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}
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define half @vpreduce_fminimum_nnan_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fminimum_nnan_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vfredmin.vs v9, v8, v9, v0.t
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; ZVFH-NEXT: vfmv.f.s fa0, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vpreduce_fminimum_nnan_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
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; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v8, v0.t
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZVFHMIN-NEXT: ret
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%s = call nnan half @llvm.vp.reduce.fminimum.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret half %s
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}
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define half @vpreduce_fmaximum_nnan_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; ZVFH-LABEL: vpreduce_fmaximum_nnan_nxv4f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma
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; ZVFH-NEXT: vfmv.s.f v9, fa0
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; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFH-NEXT: vfredmax.vs v9, v8, v9, v0.t
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; ZVFH-NEXT: vfmv.f.s fa0, v9
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vpreduce_fmaximum_nnan_nxv4f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
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; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfmv.s.f v8, fa5
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; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v8, v0.t
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; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
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|
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
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|
; ZVFHMIN-NEXT: ret
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%s = call nnan half @llvm.vp.reduce.fmaximum.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)
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|
ret half %s
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|
}
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