TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+m,+v \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+m,+v \
; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64

define signext i8 @vreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_umax_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_smax_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_smax_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_umin_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_smin_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_smin_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_and_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_or_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_xor_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_umax_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_smax_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_smax_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_umin_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_smin_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_smin_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_and_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_or_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_xor_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_add_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_add_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_umax_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_smax_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_smax_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_umin_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_smin_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_smin_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_and_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_and_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_or_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_or_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_xor_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i16 @vreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vwreduce_add_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vwreduce_add_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 1 x i8> %v to <vscale x 1 x i16>
  %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %e)
  ret i16 %red
}

define signext i16 @vwreduce_uadd_nxv1i8(<vscale x 1 x i8> %v) {
; CHECK-LABEL: vwreduce_uadd_nxv1i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 1 x i8> %v to <vscale x 1 x i16>
  %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %e)
  ret i16 %red
}

define signext i16 @vreduce_umax_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_smax_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_smax_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_umin_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_smin_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_smin_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_and_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_or_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_xor_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_add_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vwreduce_add_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vwreduce_add_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>
  %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %e)
  ret i16 %red
}

define signext i16 @vwreduce_uadd_nxv2i8(<vscale x 2 x i8> %v) {
; CHECK-LABEL: vwreduce_uadd_nxv2i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>
  %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %e)
  ret i16 %red
}

define signext i16 @vreduce_umax_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_smax_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_smax_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_umin_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_smin_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_smin_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_and_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_or_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_xor_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_add_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_add_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i16 @vwreduce_add_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vwreduce_add_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 4 x i8> %v to <vscale x 4 x i16>
  %red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %e)
  ret i16 %red
}

define signext i16 @vwreduce_uadd_nxv4i8(<vscale x 4 x i8> %v) {
; CHECK-LABEL: vwreduce_uadd_nxv4i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 4 x i8> %v to <vscale x 4 x i16>
  %red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %e)
  ret i16 %red
}

define signext i16 @vreduce_umax_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.umax.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_smax_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_smax_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.smax.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_umin_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.umin.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_smin_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_smin_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.smin.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_and_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_and_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.and.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_or_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_or_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.or.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_xor_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.xor.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i32 @vreduce_add_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vwreduce_add_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vwreduce_add_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 1 x i16> %v to <vscale x 1 x i32>
  %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %e)
  ret i32 %red
}

define signext i32 @vwreduce_uadd_nxv1i16(<vscale x 1 x i16> %v) {
; CHECK-LABEL: vwreduce_uadd_nxv1i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = zext <vscale x 1 x i16> %v to <vscale x 1 x i32>
  %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %e)
  ret i32 %red
}

define signext i32 @vreduce_umax_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_smax_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_smax_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_umin_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_smin_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_smin_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_and_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_or_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_xor_nxv1i32(<vscale x 1 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv1i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_add_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vwreduce_add_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vwreduce_add_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 2 x i16> %v to <vscale x 2 x i32>
  %red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %e)
  ret i32 %red
}

define signext i32 @vwreduce_uadd_nxv2i16(<vscale x 2 x i16> %v) {
; CHECK-LABEL: vwreduce_uadd_nxv2i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = zext <vscale x 2 x i16> %v to <vscale x 2 x i32>
  %red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %e)
  ret i32 %red
}

define signext i32 @vreduce_umax_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_smax_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_smax_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_umin_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_smin_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_smin_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_and_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_or_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_xor_nxv2i32(<vscale x 2 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_add_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vmv.s.x v10, zero
; CHECK-NEXT:    vredsum.vs v8, v8, v10
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define signext i32 @vwreduce_add_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vwreduce_add_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vwredsum.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = sext <vscale x 4 x i16> %v to <vscale x 4 x i32>
  %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %e)
  ret i32 %red
}

define signext i32 @vwreduce_uadd_nxv4i16(<vscale x 4 x i16> %v) {
; CHECK-LABEL: vwreduce_uadd_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv.s.x v9, zero
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vwredsumu.vs v8, v8, v9
; CHECK-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %e = zext <vscale x 4 x i16> %v to <vscale x 4 x i32>
  %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %e)
  ret i32 %red
}

define signext i32 @vreduce_umax_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_umax_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vredmaxu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_smax_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_smax_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vredmax.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_umin_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_umin_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vredminu.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_smin_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_smin_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vredmin.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_and_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_and_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vredand.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_or_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_or_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vredor.vs v8, v8, v8
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_xor_nxv4i32(<vscale x 4 x i32> %v) {
; CHECK-LABEL: vreduce_xor_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vmv.s.x v10, zero
; CHECK-NEXT:    vredxor.vs v8, v8, v10
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define i64 @vreduce_add_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_add_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vmv.s.x v9, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vredsum.vs v8, v8, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_add_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.s.x v9, zero
; RV64-NEXT:    vredsum.vs v8, v8, v9
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vwreduce_add_nxv1i32(<vscale x 1 x i32> %v) {
; RV32-LABEL: vwreduce_add_nxv1i32:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.s.x v9, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; RV32-NEXT:    vwredsum.vs v8, v8, v9
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vwreduce_add_nxv1i32:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.s.x v9, zero
; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64-NEXT:    vwredsum.vs v8, v8, v9
; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %e = sext <vscale x 1 x i32> %v to <vscale x 1 x i64>
  %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %e)
  ret i64 %red
}

define i64 @vwreduce_uadd_nxv1i32(<vscale x 1 x i32> %v) {
; RV32-LABEL: vwreduce_uadd_nxv1i32:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.s.x v9, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; RV32-NEXT:    vwredsumu.vs v8, v8, v9
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vwreduce_uadd_nxv1i32:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.s.x v9, zero
; RV64-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; RV64-NEXT:    vwredsumu.vs v8, v8, v9
; RV64-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %e = zext <vscale x 1 x i32> %v to <vscale x 1 x i64>
  %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %e)
  ret i64 %red
}

define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_umax_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vredmaxu.vs v8, v8, v8
; RV32-NEXT:    li a0, 32
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a1, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_umax_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vredmaxu.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_smax_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vredmax.vs v8, v8, v8
; RV32-NEXT:    li a0, 32
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a1, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_smax_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vredmax.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_umin_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vredminu.vs v8, v8, v8
; RV32-NEXT:    li a0, 32
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a1, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_umin_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vredminu.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_smin_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vredmin.vs v8, v8, v8
; RV32-NEXT:    li a0, 32
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a1, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_smin_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vredmin.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_and_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vredand.vs v8, v8, v8
; RV32-NEXT:    li a0, 32
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a1, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_and_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vredand.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_or_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vredor.vs v8, v8, v8
; RV32-NEXT:    li a0, 32
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a1, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_or_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vredor.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_xor_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_xor_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vmv.s.x v9, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vredxor.vs v8, v8, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_xor_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.s.x v9, zero
; RV64-NEXT:    vredxor.vs v8, v8, v9
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_add_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vmv.s.x v10, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vredsum.vs v8, v8, v10
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_add_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vmv.s.x v10, zero
; RV64-NEXT:    vredsum.vs v8, v8, v10
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vwreduce_add_nxv2i32(<vscale x 2 x i32> %v) {
; RV32-LABEL: vwreduce_add_nxv2i32:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.s.x v9, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT:    vwredsum.vs v8, v8, v9
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vwreduce_add_nxv2i32:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.s.x v9, zero
; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT:    vwredsum.vs v8, v8, v9
; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>
  %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %e)
  ret i64 %red
}

define i64 @vwreduce_uadd_nxv2i32(<vscale x 2 x i32> %v) {
; RV32-LABEL: vwreduce_uadd_nxv2i32:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.s.x v9, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT:    vwredsumu.vs v8, v8, v9
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vwreduce_uadd_nxv2i32:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.s.x v9, zero
; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT:    vwredsumu.vs v8, v8, v9
; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %e = zext <vscale x 2 x i32> %v to <vscale x 2 x i64>
  %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %e)
  ret i64 %red
}

define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_umax_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vredmaxu.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_umax_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vredmaxu.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_smax_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vredmax.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_smax_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vredmax.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_umin_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vredminu.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_umin_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vredminu.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_smin_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vredmin.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_smin_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vredmin.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_and_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vredand.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_and_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vredand.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_or_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vredor.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_or_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vredor.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_xor_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV32-NEXT:    vmv.s.x v10, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vredxor.vs v8, v8, v10
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_xor_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; RV64-NEXT:    vmv.s.x v10, zero
; RV64-NEXT:    vredxor.vs v8, v8, v10
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_add_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT:    vmv.s.x v12, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vredsum.vs v8, v8, v12
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_add_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64-NEXT:    vmv.s.x v12, zero
; RV64-NEXT:    vredsum.vs v8, v8, v12
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

define i64 @vwreduce_add_nxv4i32(<vscale x 4 x i32> %v) {
; RV32-LABEL: vwreduce_add_nxv4i32:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.s.x v10, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; RV32-NEXT:    vwredsum.vs v8, v8, v10
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vwreduce_add_nxv4i32:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.s.x v10, zero
; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT:    vwredsum.vs v8, v8, v10
; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %e = sext <vscale x 4 x i32> %v to <vscale x 4 x i64>
  %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %e)
  ret i64 %red
}

define i64 @vwreduce_uadd_nxv4i32(<vscale x 4 x i32> %v) {
; RV32-LABEL: vwreduce_uadd_nxv4i32:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.s.x v10, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; RV32-NEXT:    vwredsumu.vs v8, v8, v10
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vwreduce_uadd_nxv4i32:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmv.s.x v10, zero
; RV64-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; RV64-NEXT:    vwredsumu.vs v8, v8, v10
; RV64-NEXT:    vsetvli zero, zero, e64, m4, ta, ma
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %e = zext <vscale x 4 x i32> %v to <vscale x 4 x i64>
  %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %e)
  ret i64 %red
}

define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_umax_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT:    vredmaxu.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_umax_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64-NEXT:    vredmaxu.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_smax_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT:    vredmax.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_smax_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64-NEXT:    vredmax.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_umin_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT:    vredminu.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_umin_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64-NEXT:    vredminu.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_smin_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT:    vredmin.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_smin_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64-NEXT:    vredmin.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_and_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT:    vredand.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_and_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64-NEXT:    vredand.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_or_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT:    vredor.vs v8, v8, v8
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_or_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64-NEXT:    vredor.vs v8, v8, v8
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_xor_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV32-NEXT:    vmv.s.x v12, zero
; RV32-NEXT:    li a1, 32
; RV32-NEXT:    vredxor.vs v8, v8, v12
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vsrl.vx v8, v8, a1
; RV32-NEXT:    vmv.x.s a1, v8
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_xor_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; RV64-NEXT:    vmv.s.x v12, zero
; RV64-NEXT:    vredxor.vs v8, v8, v12
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

define signext i8 @vreduce_mul_nxv1i8(<vscale x 1 x i8> %v) {
; RV32-LABEL: vreduce_mul_nxv1i8:
; RV32:       # %bb.0:
; RV32-NEXT:    li a0, 0
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 3
; RV32-NEXT:    li a1, 1
; RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT:  .LBB114_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a0, a0, 1
; RV32-NEXT:    mul a1, a1, a3
; RV32-NEXT:    bne a0, a2, .LBB114_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    slli a0, a1, 24
; RV32-NEXT:    srai a0, a0, 24
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv1i8:
; RV64:       # %bb.0:
; RV64-NEXT:    li a0, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 3
; RV64-NEXT:    li a1, 1
; RV64-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT:  .LBB114_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a0
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a0, a0, 1
; RV64-NEXT:    mul a1, a1, a3
; RV64-NEXT:    bne a0, a2, .LBB114_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    slli a0, a1, 56
; RV64-NEXT:    srai a0, a0, 56
; RV64-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.mul.nxv1i8(<vscale x 1 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_mul_nxv2i8(<vscale x 2 x i8> %v) {
; RV32-LABEL: vreduce_mul_nxv2i8:
; RV32:       # %bb.0:
; RV32-NEXT:    li a0, 0
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 2
; RV32-NEXT:    li a1, 1
; RV32-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
; RV32-NEXT:  .LBB115_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a0, a0, 1
; RV32-NEXT:    mul a1, a1, a3
; RV32-NEXT:    bne a0, a2, .LBB115_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    slli a0, a1, 24
; RV32-NEXT:    srai a0, a0, 24
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv2i8:
; RV64:       # %bb.0:
; RV64-NEXT:    li a0, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 2
; RV64-NEXT:    li a1, 1
; RV64-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
; RV64-NEXT:  .LBB115_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a0
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a0, a0, 1
; RV64-NEXT:    mul a1, a1, a3
; RV64-NEXT:    bne a0, a2, .LBB115_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    slli a0, a1, 56
; RV64-NEXT:    srai a0, a0, 56
; RV64-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.mul.nxv2i8(<vscale x 2 x i8> %v)
  ret i8 %red
}

define signext i8 @vreduce_mul_nxv4i8(<vscale x 4 x i8> %v) {
; RV32-LABEL: vreduce_mul_nxv4i8:
; RV32:       # %bb.0:
; RV32-NEXT:    li a0, 0
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 1
; RV32-NEXT:    li a1, 1
; RV32-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma
; RV32-NEXT:  .LBB116_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a0, a0, 1
; RV32-NEXT:    mul a1, a1, a3
; RV32-NEXT:    bne a0, a2, .LBB116_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    slli a0, a1, 24
; RV32-NEXT:    srai a0, a0, 24
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv4i8:
; RV64:       # %bb.0:
; RV64-NEXT:    li a0, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 1
; RV64-NEXT:    li a1, 1
; RV64-NEXT:    vsetivli zero, 1, e8, mf2, ta, ma
; RV64-NEXT:  .LBB116_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a0
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a0, a0, 1
; RV64-NEXT:    mul a1, a1, a3
; RV64-NEXT:    bne a0, a2, .LBB116_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    slli a0, a1, 56
; RV64-NEXT:    srai a0, a0, 56
; RV64-NEXT:    ret
  %red = call i8 @llvm.vector.reduce.mul.nxv4i8(<vscale x 4 x i8> %v)
  ret i8 %red
}

define signext i16 @vreduce_mul_nxv1i16(<vscale x 1 x i16> %v) {
; RV32-LABEL: vreduce_mul_nxv1i16:
; RV32:       # %bb.0:
; RV32-NEXT:    li a0, 0
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 3
; RV32-NEXT:    li a1, 1
; RV32-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT:  .LBB117_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a0, a0, 1
; RV32-NEXT:    mul a1, a1, a3
; RV32-NEXT:    bne a0, a2, .LBB117_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    slli a0, a1, 16
; RV32-NEXT:    srai a0, a0, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv1i16:
; RV64:       # %bb.0:
; RV64-NEXT:    li a0, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 3
; RV64-NEXT:    li a1, 1
; RV64-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT:  .LBB117_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a0
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a0, a0, 1
; RV64-NEXT:    mul a1, a1, a3
; RV64-NEXT:    bne a0, a2, .LBB117_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    slli a0, a1, 48
; RV64-NEXT:    srai a0, a0, 48
; RV64-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.mul.nxv1i16(<vscale x 1 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_mul_nxv2i16(<vscale x 2 x i16> %v) {
; RV32-LABEL: vreduce_mul_nxv2i16:
; RV32:       # %bb.0:
; RV32-NEXT:    li a0, 0
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 2
; RV32-NEXT:    li a1, 1
; RV32-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
; RV32-NEXT:  .LBB118_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a0, a0, 1
; RV32-NEXT:    mul a1, a1, a3
; RV32-NEXT:    bne a0, a2, .LBB118_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    slli a0, a1, 16
; RV32-NEXT:    srai a0, a0, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv2i16:
; RV64:       # %bb.0:
; RV64-NEXT:    li a0, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 2
; RV64-NEXT:    li a1, 1
; RV64-NEXT:    vsetivli zero, 1, e16, mf2, ta, ma
; RV64-NEXT:  .LBB118_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a0
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a0, a0, 1
; RV64-NEXT:    mul a1, a1, a3
; RV64-NEXT:    bne a0, a2, .LBB118_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    slli a0, a1, 48
; RV64-NEXT:    srai a0, a0, 48
; RV64-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.mul.nxv2i16(<vscale x 2 x i16> %v)
  ret i16 %red
}

define signext i16 @vreduce_mul_nxv4i16(<vscale x 4 x i16> %v) {
; RV32-LABEL: vreduce_mul_nxv4i16:
; RV32:       # %bb.0:
; RV32-NEXT:    li a0, 0
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 1
; RV32-NEXT:    li a1, 1
; RV32-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV32-NEXT:  .LBB119_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a0, a0, 1
; RV32-NEXT:    mul a1, a1, a3
; RV32-NEXT:    bne a0, a2, .LBB119_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    slli a0, a1, 16
; RV32-NEXT:    srai a0, a0, 16
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv4i16:
; RV64:       # %bb.0:
; RV64-NEXT:    li a0, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 1
; RV64-NEXT:    li a1, 1
; RV64-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; RV64-NEXT:  .LBB119_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a0
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a0, a0, 1
; RV64-NEXT:    mul a1, a1, a3
; RV64-NEXT:    bne a0, a2, .LBB119_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    slli a0, a1, 48
; RV64-NEXT:    srai a0, a0, 48
; RV64-NEXT:    ret
  %red = call i16 @llvm.vector.reduce.mul.nxv4i16(<vscale x 4 x i16> %v)
  ret i16 %red
}

define signext i32 @vreduce_mul_nxv1i32(<vscale x 1 x i32> %v) {
; RV32-LABEL: vreduce_mul_nxv1i32:
; RV32:       # %bb.0:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 3
; RV32-NEXT:    li a0, 1
; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT:  .LBB120_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a1
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a1, a1, 1
; RV32-NEXT:    mul a0, a0, a3
; RV32-NEXT:    bne a1, a2, .LBB120_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv1i32:
; RV64:       # %bb.0:
; RV64-NEXT:    li a1, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 3
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
; RV64-NEXT:  .LBB120_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a1
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a1, a1, 1
; RV64-NEXT:    mulw a0, a0, a3
; RV64-NEXT:    bne a1, a2, .LBB120_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_mul_nxv2i32(<vscale x 2 x i32> %v) {
; RV32-LABEL: vreduce_mul_nxv2i32:
; RV32:       # %bb.0:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 2
; RV32-NEXT:    li a0, 1
; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT:  .LBB121_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a1
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a1, a1, 1
; RV32-NEXT:    mul a0, a0, a3
; RV32-NEXT:    bne a1, a2, .LBB121_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv2i32:
; RV64:       # %bb.0:
; RV64-NEXT:    li a1, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 2
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT:  .LBB121_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a1
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a1, a1, 1
; RV64-NEXT:    mulw a0, a0, a3
; RV64-NEXT:    bne a1, a2, .LBB121_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_mul_nxv4i32(<vscale x 4 x i32> %v) {
; RV32-LABEL: vreduce_mul_nxv4i32:
; RV32:       # %bb.0:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    srli a2, a2, 2
; RV32-NEXT:    li a0, 1
; RV32-NEXT:  .LBB122_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT:    vslidedown.vx v9, v8, a1
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a1, a1, 1
; RV32-NEXT:    mul a0, a0, a3
; RV32-NEXT:    bne a1, a2, .LBB122_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv4i32:
; RV64:       # %bb.0:
; RV64-NEXT:    li a1, 0
; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 2
; RV64-NEXT:    li a0, 1
; RV64-NEXT:  .LBB122_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT:    vslidedown.vx v9, v8, a1
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a1, a1, 1
; RV64-NEXT:    mulw a0, a0, a3
; RV64-NEXT:    bne a1, a2, .LBB122_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define i64 @vreduce_mul_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_mul_nxv1i64:
; RV32:       # %bb.0:
; RV32-NEXT:    li a2, 0
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    csrr a3, vlenb
; RV32-NEXT:    li a0, 1
; RV32-NEXT:    srli a3, a3, 3
; RV32-NEXT:    li a4, 32
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:  .LBB123_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v9, v8, a2
; RV32-NEXT:    addi a2, a2, 1
; RV32-NEXT:    vsrl.vx v10, v9, a4
; RV32-NEXT:    vmv.x.s a5, v9
; RV32-NEXT:    vmv.x.s a6, v10
; RV32-NEXT:    mulhu a7, a0, a5
; RV32-NEXT:    mul a1, a1, a5
; RV32-NEXT:    mul a6, a0, a6
; RV32-NEXT:    add a1, a7, a1
; RV32-NEXT:    add a1, a1, a6
; RV32-NEXT:    mul a0, a0, a5
; RV32-NEXT:    bne a2, a3, .LBB123_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv1i64:
; RV64:       # %bb.0:
; RV64-NEXT:    li a1, 0
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 3
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT:  .LBB123_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v9, v8, a1
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a1, a1, 1
; RV64-NEXT:    mul a0, a0, a3
; RV64-NEXT:    bne a1, a2, .LBB123_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.mul.nxv1i64(<vscale x 1 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_mul_nxv2i64(<vscale x 2 x i64> %v) {
; RV32-LABEL: vreduce_mul_nxv2i64:
; RV32:       # %bb.0:
; RV32-NEXT:    li a2, 0
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    csrr a3, vlenb
; RV32-NEXT:    li a0, 1
; RV32-NEXT:    srli a3, a3, 3
; RV32-NEXT:    li a4, 32
; RV32-NEXT:  .LBB124_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vslidedown.vx v9, v8, a2
; RV32-NEXT:    addi a2, a2, 1
; RV32-NEXT:    vsrl.vx v10, v9, a4
; RV32-NEXT:    vmv.x.s a5, v9
; RV32-NEXT:    vmv.x.s a6, v10
; RV32-NEXT:    mulhu a7, a0, a5
; RV32-NEXT:    mul a1, a1, a5
; RV32-NEXT:    mul a6, a0, a6
; RV32-NEXT:    add a1, a7, a1
; RV32-NEXT:    add a1, a1, a6
; RV32-NEXT:    mul a0, a0, a5
; RV32-NEXT:    bne a2, a3, .LBB124_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv2i64:
; RV64:       # %bb.0:
; RV64-NEXT:    li a1, 0
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    srli a2, a2, 3
; RV64-NEXT:    li a0, 1
; RV64-NEXT:  .LBB124_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT:    vslidedown.vx v9, v8, a1
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a1, a1, 1
; RV64-NEXT:    mul a0, a0, a3
; RV64-NEXT:    bne a1, a2, .LBB124_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.mul.nxv2i64(<vscale x 2 x i64> %v)
  ret i64 %red
}

define i64 @vreduce_mul_nxv4i64(<vscale x 4 x i64> %v) {
; RV32-LABEL: vreduce_mul_nxv4i64:
; RV32:       # %bb.0:
; RV32-NEXT:    li a2, 0
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vmul.vv v9, v10, v11
; RV32-NEXT:    csrr a3, vlenb
; RV32-NEXT:    li a0, 1
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    srli a3, a3, 3
; RV32-NEXT:    li a4, 32
; RV32-NEXT:  .LBB125_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT:    vslidedown.vx v9, v8, a2
; RV32-NEXT:    addi a2, a2, 1
; RV32-NEXT:    vsrl.vx v10, v9, a4
; RV32-NEXT:    vmv.x.s a5, v9
; RV32-NEXT:    vmv.x.s a6, v10
; RV32-NEXT:    mulhu a7, a0, a5
; RV32-NEXT:    mul a1, a1, a5
; RV32-NEXT:    mul a6, a0, a6
; RV32-NEXT:    add a1, a7, a1
; RV32-NEXT:    add a1, a1, a6
; RV32-NEXT:    mul a0, a0, a5
; RV32-NEXT:    bne a2, a3, .LBB125_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv4i64:
; RV64:       # %bb.0:
; RV64-NEXT:    li a1, 0
; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vmul.vv v9, v10, v11
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    srli a2, a2, 3
; RV64-NEXT:    li a0, 1
; RV64-NEXT:  .LBB125_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT:    vslidedown.vx v9, v8, a1
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a1, a1, 1
; RV64-NEXT:    mul a0, a0, a3
; RV64-NEXT:    bne a1, a2, .LBB125_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    ret
  %red = call i64 @llvm.vector.reduce.mul.nxv4i64(<vscale x 4 x i64> %v)
  ret i64 %red
}

; Non-power-of-two number of M1 pieces; should not be split by buildMulTree.
define signext i32 @vreduce_mul_nxv6i32(<vscale x 6 x i32> %v) {
; RV32-LABEL: vreduce_mul_nxv6i32:
; RV32:       # %bb.0:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    csrr a0, vlenb
; RV32-NEXT:    srli a2, a0, 2
; RV32-NEXT:    sub a2, a0, a2
; RV32-NEXT:    li a0, 1
; RV32-NEXT:    vsetivli zero, 1, e32, m4, ta, ma
; RV32-NEXT:  .LBB126_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vslidedown.vx v12, v8, a1
; RV32-NEXT:    vmv.x.s a3, v12
; RV32-NEXT:    addi a1, a1, 1
; RV32-NEXT:    mul a0, a0, a3
; RV32-NEXT:    bne a1, a2, .LBB126_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv6i32:
; RV64:       # %bb.0:
; RV64-NEXT:    li a1, 0
; RV64-NEXT:    csrr a0, vlenb
; RV64-NEXT:    srli a2, a0, 2
; RV64-NEXT:    sub a2, a0, a2
; RV64-NEXT:    li a0, 1
; RV64-NEXT:    vsetivli zero, 1, e32, m4, ta, ma
; RV64-NEXT:  .LBB126_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vslidedown.vx v12, v8, a1
; RV64-NEXT:    vmv.x.s a3, v12
; RV64-NEXT:    addi a1, a1, 1
; RV64-NEXT:    mulw a0, a0, a3
; RV64-NEXT:    bne a1, a2, .LBB126_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv6i32(<vscale x 6 x i32> %v)
  ret i32 %red
}

; Illegal element type; should not be split by buildMulTree.
define signext i31 @vreduce_mul_nxv8i31(<vscale x 8 x i31> %v) {
; RV32-LABEL: vreduce_mul_nxv8i31:
; RV32:       # %bb.0:
; RV32-NEXT:    li a0, 0
; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vmul.vv v9, v10, v11
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    srli a2, a2, 2
; RV32-NEXT:    li a1, 1
; RV32-NEXT:  .LBB127_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT:    vslidedown.vx v9, v8, a0
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a0, a0, 1
; RV32-NEXT:    mul a1, a1, a3
; RV32-NEXT:    bne a0, a2, .LBB127_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    slli a0, a1, 1
; RV32-NEXT:    srai a0, a0, 1
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv8i31:
; RV64:       # %bb.0:
; RV64-NEXT:    li a0, 0
; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vmul.vv v9, v10, v11
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    srli a2, a2, 2
; RV64-NEXT:    li a1, 1
; RV64-NEXT:  .LBB127_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT:    vslidedown.vx v9, v8, a0
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a0, a0, 1
; RV64-NEXT:    mul a1, a1, a3
; RV64-NEXT:    bne a0, a2, .LBB127_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    slli a0, a1, 33
; RV64-NEXT:    srai a0, a0, 33
; RV64-NEXT:    ret
  %red = call i31 @llvm.vector.reduce.mul.nxv8i31(<vscale x 8 x i31> %v)
  ret i31 %red
}

define signext i32 @vreduce_mul_nxv32i32(<vscale x 32 x i32> %v) {
; RV32-LABEL: vreduce_mul_nxv32i32:
; RV32:       # %bb.0:
; RV32-NEXT:    li a1, 0
; RV32-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vmul.vv v9, v10, v11
; RV32-NEXT:    vmul.vv v10, v12, v13
; RV32-NEXT:    vmul.vv v11, v14, v15
; RV32-NEXT:    vmul.vv v12, v16, v17
; RV32-NEXT:    vmul.vv v13, v18, v19
; RV32-NEXT:    vmul.vv v14, v20, v21
; RV32-NEXT:    vmul.vv v15, v22, v23
; RV32-NEXT:    csrr a2, vlenb
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vmul.vv v9, v10, v11
; RV32-NEXT:    vmul.vv v10, v12, v13
; RV32-NEXT:    vmul.vv v11, v14, v15
; RV32-NEXT:    srli a2, a2, 2
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vmul.vv v9, v10, v11
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    li a0, 1
; RV32-NEXT:  .LBB128_1: # %rdx.loop
; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
; RV32-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT:    vslidedown.vx v9, v8, a1
; RV32-NEXT:    vmv.x.s a3, v9
; RV32-NEXT:    addi a1, a1, 1
; RV32-NEXT:    mul a0, a0, a3
; RV32-NEXT:    bne a1, a2, .LBB128_1
; RV32-NEXT:  # %bb.2: # %rdx.exit
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv32i32:
; RV64:       # %bb.0:
; RV64-NEXT:    li a1, 0
; RV64-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vmul.vv v9, v10, v11
; RV64-NEXT:    vmul.vv v10, v12, v13
; RV64-NEXT:    vmul.vv v11, v14, v15
; RV64-NEXT:    vmul.vv v12, v16, v17
; RV64-NEXT:    vmul.vv v13, v18, v19
; RV64-NEXT:    vmul.vv v14, v20, v21
; RV64-NEXT:    vmul.vv v15, v22, v23
; RV64-NEXT:    csrr a2, vlenb
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vmul.vv v9, v10, v11
; RV64-NEXT:    vmul.vv v10, v12, v13
; RV64-NEXT:    vmul.vv v11, v14, v15
; RV64-NEXT:    srli a2, a2, 2
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vmul.vv v9, v10, v11
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    li a0, 1
; RV64-NEXT:  .LBB128_1: # %rdx.loop
; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT:    vslidedown.vx v9, v8, a1
; RV64-NEXT:    vmv.x.s a3, v9
; RV64-NEXT:    addi a1, a1, 1
; RV64-NEXT:    mulw a0, a0, a3
; RV64-NEXT:    bne a1, a2, .LBB128_1
; RV64-NEXT:  # %bb.2: # %rdx.exit
; RV64-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv32i32(<vscale x 32 x i32> %v)
  ret i32 %red
}

; With known VLEN, scalable mul reductions can use fixed-vector shuffle
; reduction instead of a scalar loop.

define signext i32 @vreduce_mul_nxv2i32_exact_vlen(<vscale x 2 x i32> %v) vscale_range(2,2) {
; CHECK-LABEL: vreduce_mul_nxv2i32_exact_vlen:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vslidedown.vi v9, v8, 2
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vrgather.vi v9, v8, 1
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv2i32(<vscale x 2 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_mul_nxv4i32_exact_vlen(<vscale x 4 x i32> %v) vscale_range(2,2) {
; CHECK-LABEL: vreduce_mul_nxv4i32_exact_vlen:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vslidedown.vi v9, v8, 2
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vrgather.vi v9, v8, 1
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv4i32(<vscale x 4 x i32> %v)
  ret i32 %red
}

define signext i32 @vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen(<vscale x 8 x i32> %v) vscale_range(2,2) {
; CHECK-LABEL: vreduce_mul_nxv6i32_from_nxv8i32_exact_vlen:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vslidedown.vi v11, v10, 3
; CHECK-NEXT:    vslidedown.vi v12, v10, 2
; CHECK-NEXT:    vslidedown.vi v13, v10, 1
; CHECK-NEXT:    vmv.x.s a0, v10
; CHECK-NEXT:    vslidedown.vi v10, v8, 3
; CHECK-NEXT:    vslidedown.vi v14, v8, 2
; CHECK-NEXT:    vslidedown.vi v15, v8, 1
; CHECK-NEXT:    vmv.x.s a1, v8
; CHECK-NEXT:    vslidedown.vi v8, v9, 3
; CHECK-NEXT:    vslidedown.vi v16, v9, 2
; CHECK-NEXT:    vmv.x.s a2, v9
; CHECK-NEXT:    vslidedown.vi v9, v9, 1
; CHECK-NEXT:    vmv.x.s a3, v11
; CHECK-NEXT:    vmv.x.s a4, v12
; CHECK-NEXT:    vmv.x.s a5, v13
; CHECK-NEXT:    vmv.x.s a6, v10
; CHECK-NEXT:    vmv.x.s a7, v14
; CHECK-NEXT:    vmv.x.s t0, v15
; CHECK-NEXT:    vmv.x.s t1, v8
; CHECK-NEXT:    vmv.x.s t2, v16
; CHECK-NEXT:    vmv.x.s t3, v9
; CHECK-NEXT:    vmv.v.x v8, a2
; CHECK-NEXT:    vmv.v.x v9, a1
; CHECK-NEXT:    vmv.v.x v10, a0
; CHECK-NEXT:    vslide1down.vx v8, v8, t3
; CHECK-NEXT:    vslide1down.vx v9, v9, t0
; CHECK-NEXT:    vslide1down.vx v10, v10, a5
; CHECK-NEXT:    vslide1down.vx v8, v8, t2
; CHECK-NEXT:    vslide1down.vx v11, v9, a7
; CHECK-NEXT:    vslide1down.vx v10, v10, a4
; CHECK-NEXT:    vslide1down.vx v9, v8, t1
; CHECK-NEXT:    vslide1down.vx v10, v10, a3
; CHECK-NEXT:    vslide1down.vx v8, v11, a6
; CHECK-NEXT:    vmv.v.i v11, 1
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v10
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT:    vslidedown.vi v9, v8, 2
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vslidedown.vi v9, v8, 1
; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %sub = call <vscale x 6 x i32> @llvm.vector.extract.nxv6i32.nxv8i32(<vscale x 8 x i32> %v, i64 0)
  %red = call i32 @llvm.vector.reduce.mul.nxv6i32(<vscale x 6 x i32> %sub)
  ret i32 %red
}

define signext i32 @vreduce_mul_nxv6i32_exact_vlen(<vscale x 6 x i32> %v) vscale_range(2,2) {
; CHECK-LABEL: vreduce_mul_nxv6i32_exact_vlen:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vslidedown.vi v11, v10, 3
; CHECK-NEXT:    vslidedown.vi v12, v10, 2
; CHECK-NEXT:    vslidedown.vi v13, v10, 1
; CHECK-NEXT:    vmv.x.s a0, v10
; CHECK-NEXT:    vslidedown.vi v10, v8, 3
; CHECK-NEXT:    vslidedown.vi v14, v8, 2
; CHECK-NEXT:    vslidedown.vi v15, v8, 1
; CHECK-NEXT:    vmv.x.s a1, v8
; CHECK-NEXT:    vslidedown.vi v8, v9, 3
; CHECK-NEXT:    vslidedown.vi v16, v9, 2
; CHECK-NEXT:    vmv.x.s a2, v9
; CHECK-NEXT:    vslidedown.vi v9, v9, 1
; CHECK-NEXT:    vmv.x.s a3, v11
; CHECK-NEXT:    vmv.x.s a4, v12
; CHECK-NEXT:    vmv.x.s a5, v13
; CHECK-NEXT:    vmv.x.s a6, v10
; CHECK-NEXT:    vmv.x.s a7, v14
; CHECK-NEXT:    vmv.x.s t0, v15
; CHECK-NEXT:    vmv.x.s t1, v8
; CHECK-NEXT:    vmv.x.s t2, v16
; CHECK-NEXT:    vmv.x.s t3, v9
; CHECK-NEXT:    vmv.v.x v8, a2
; CHECK-NEXT:    vmv.v.x v9, a1
; CHECK-NEXT:    vmv.v.x v10, a0
; CHECK-NEXT:    vslide1down.vx v8, v8, t3
; CHECK-NEXT:    vslide1down.vx v9, v9, t0
; CHECK-NEXT:    vslide1down.vx v10, v10, a5
; CHECK-NEXT:    vslide1down.vx v8, v8, t2
; CHECK-NEXT:    vslide1down.vx v11, v9, a7
; CHECK-NEXT:    vslide1down.vx v10, v10, a4
; CHECK-NEXT:    vslide1down.vx v9, v8, t1
; CHECK-NEXT:    vslide1down.vx v10, v10, a3
; CHECK-NEXT:    vslide1down.vx v8, v11, a6
; CHECK-NEXT:    vmv.v.i v11, 1
; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v10
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vsetivli zero, 2, e32, m1, ta, ma
; CHECK-NEXT:    vslidedown.vi v9, v8, 2
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vslidedown.vi v9, v8, 1
; CHECK-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv6i32(<vscale x 6 x i32> %v)
  ret i32 %red
}

define signext i31 @vreduce_mul_nxv8i31_exact_vlen(<vscale x 8 x i31> %v) vscale_range(2,2) {
; RV32-LABEL: vreduce_mul_nxv8i31_exact_vlen:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    sw s0, 12(sp) # 4-byte Folded Spill
; RV32-NEXT:    .cfi_offset s0, -4
; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT:    vslidedown.vi v12, v11, 3
; RV32-NEXT:    vslidedown.vi v13, v11, 2
; RV32-NEXT:    vslidedown.vi v14, v11, 1
; RV32-NEXT:    vmv.x.s a0, v11
; RV32-NEXT:    vslidedown.vi v11, v10, 3
; RV32-NEXT:    vslidedown.vi v15, v10, 2
; RV32-NEXT:    vslidedown.vi v16, v10, 1
; RV32-NEXT:    vmv.x.s a1, v10
; RV32-NEXT:    vslidedown.vi v10, v9, 3
; RV32-NEXT:    vslidedown.vi v17, v9, 2
; RV32-NEXT:    vslidedown.vi v18, v9, 1
; RV32-NEXT:    vmv.x.s a2, v9
; RV32-NEXT:    vslidedown.vi v9, v8, 3
; RV32-NEXT:    vslidedown.vi v19, v8, 2
; RV32-NEXT:    vmv.x.s a3, v8
; RV32-NEXT:    vslidedown.vi v8, v8, 1
; RV32-NEXT:    vmv.x.s a4, v12
; RV32-NEXT:    vmv.x.s a5, v13
; RV32-NEXT:    vmv.x.s a6, v14
; RV32-NEXT:    vmv.x.s a7, v11
; RV32-NEXT:    vmv.x.s t0, v15
; RV32-NEXT:    vmv.x.s t1, v16
; RV32-NEXT:    vmv.x.s t2, v10
; RV32-NEXT:    vmv.x.s t3, v17
; RV32-NEXT:    vmv.x.s t4, v18
; RV32-NEXT:    vmv.x.s t5, v9
; RV32-NEXT:    vmv.x.s t6, v19
; RV32-NEXT:    vmv.x.s s0, v8
; RV32-NEXT:    vmv.v.x v8, a3
; RV32-NEXT:    vmv.v.x v9, a2
; RV32-NEXT:    vmv.v.x v10, a1
; RV32-NEXT:    vmv.v.x v11, a0
; RV32-NEXT:    vslide1down.vx v8, v8, s0
; RV32-NEXT:    vslide1down.vx v9, v9, t4
; RV32-NEXT:    vslide1down.vx v10, v10, t1
; RV32-NEXT:    vslide1down.vx v11, v11, a6
; RV32-NEXT:    vslide1down.vx v8, v8, t6
; RV32-NEXT:    vslide1down.vx v9, v9, t3
; RV32-NEXT:    vslide1down.vx v10, v10, t0
; RV32-NEXT:    vslide1down.vx v11, v11, a5
; RV32-NEXT:    vslide1down.vx v8, v8, t5
; RV32-NEXT:    vslide1down.vx v9, v9, t2
; RV32-NEXT:    vslide1down.vx v10, v10, a7
; RV32-NEXT:    vslide1down.vx v11, v11, a4
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vmul.vv v9, v10, v11
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vslidedown.vi v9, v8, 2
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vrgather.vi v9, v8, 1
; RV32-NEXT:    vmul.vv v8, v8, v9
; RV32-NEXT:    vmv.x.s a0, v8
; RV32-NEXT:    slli a0, a0, 1
; RV32-NEXT:    srai a0, a0, 1
; RV32-NEXT:    lw s0, 12(sp) # 4-byte Folded Reload
; RV32-NEXT:    .cfi_restore s0
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    .cfi_def_cfa_offset 0
; RV32-NEXT:    ret
;
; RV64-LABEL: vreduce_mul_nxv8i31_exact_vlen:
; RV64:       # %bb.0:
; RV64-NEXT:    addi sp, sp, -16
; RV64-NEXT:    .cfi_def_cfa_offset 16
; RV64-NEXT:    sd s0, 8(sp) # 8-byte Folded Spill
; RV64-NEXT:    .cfi_offset s0, -8
; RV64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT:    vslidedown.vi v12, v11, 3
; RV64-NEXT:    vslidedown.vi v13, v11, 2
; RV64-NEXT:    vslidedown.vi v14, v11, 1
; RV64-NEXT:    vmv.x.s a0, v11
; RV64-NEXT:    vslidedown.vi v11, v10, 3
; RV64-NEXT:    vslidedown.vi v15, v10, 2
; RV64-NEXT:    vslidedown.vi v16, v10, 1
; RV64-NEXT:    vmv.x.s a1, v10
; RV64-NEXT:    vslidedown.vi v10, v9, 3
; RV64-NEXT:    vslidedown.vi v17, v9, 2
; RV64-NEXT:    vslidedown.vi v18, v9, 1
; RV64-NEXT:    vmv.x.s a2, v9
; RV64-NEXT:    vslidedown.vi v9, v8, 3
; RV64-NEXT:    vslidedown.vi v19, v8, 2
; RV64-NEXT:    vmv.x.s a3, v8
; RV64-NEXT:    vslidedown.vi v8, v8, 1
; RV64-NEXT:    vmv.x.s a4, v12
; RV64-NEXT:    vmv.x.s a5, v13
; RV64-NEXT:    vmv.x.s a6, v14
; RV64-NEXT:    vmv.x.s a7, v11
; RV64-NEXT:    vmv.x.s t0, v15
; RV64-NEXT:    vmv.x.s t1, v16
; RV64-NEXT:    vmv.x.s t2, v10
; RV64-NEXT:    vmv.x.s t3, v17
; RV64-NEXT:    vmv.x.s t4, v18
; RV64-NEXT:    vmv.x.s t5, v9
; RV64-NEXT:    vmv.x.s t6, v19
; RV64-NEXT:    vmv.x.s s0, v8
; RV64-NEXT:    vmv.v.x v8, a3
; RV64-NEXT:    vmv.v.x v9, a2
; RV64-NEXT:    vmv.v.x v10, a1
; RV64-NEXT:    vmv.v.x v11, a0
; RV64-NEXT:    vslide1down.vx v8, v8, s0
; RV64-NEXT:    vslide1down.vx v9, v9, t4
; RV64-NEXT:    vslide1down.vx v10, v10, t1
; RV64-NEXT:    vslide1down.vx v11, v11, a6
; RV64-NEXT:    vslide1down.vx v8, v8, t6
; RV64-NEXT:    vslide1down.vx v9, v9, t3
; RV64-NEXT:    vslide1down.vx v10, v10, t0
; RV64-NEXT:    vslide1down.vx v11, v11, a5
; RV64-NEXT:    vslide1down.vx v8, v8, t5
; RV64-NEXT:    vslide1down.vx v9, v9, t2
; RV64-NEXT:    vslide1down.vx v10, v10, a7
; RV64-NEXT:    vslide1down.vx v11, v11, a4
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vmul.vv v9, v10, v11
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vslidedown.vi v9, v8, 2
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vrgather.vi v9, v8, 1
; RV64-NEXT:    vmul.vv v8, v8, v9
; RV64-NEXT:    vmv.x.s a0, v8
; RV64-NEXT:    slli a0, a0, 33
; RV64-NEXT:    srai a0, a0, 33
; RV64-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
; RV64-NEXT:    .cfi_restore s0
; RV64-NEXT:    addi sp, sp, 16
; RV64-NEXT:    .cfi_def_cfa_offset 0
; RV64-NEXT:    ret
  %red = call i31 @llvm.vector.reduce.mul.nxv8i31(<vscale x 8 x i31> %v)
  ret i31 %red
}

define signext i32 @vreduce_mul_nxv1i32_exact_vlen(<vscale x 1 x i32> %v) vscale_range(2,2) {
; CHECK-LABEL: vreduce_mul_nxv1i32_exact_vlen:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT:    vrgather.vi v9, v8, 1
; CHECK-NEXT:    vmul.vv v8, v8, v9
; CHECK-NEXT:    vmv.x.s a0, v8
; CHECK-NEXT:    ret
  %red = call i32 @llvm.vector.reduce.mul.nxv1i32(<vscale x 1 x i32> %v)
  ret i32 %red
}