derek.holloway
7502bf64a4
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1131 lines
36 KiB
LLVM
1131 lines
36 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
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define zeroext i1 @vreduce_or_nxv1i1(<vscale x 1 x i1> %v) {
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; CHECK-LABEL: vreduce_or_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.or.nxv1i1(<vscale x 1 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_xor_nxv1i1(<vscale x 1 x i1> %v) {
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; CHECK-LABEL: vreduce_xor_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.xor.nxv1i1(<vscale x 1 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) {
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; CHECK-LABEL: vreduce_and_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_umax_nxv1i1(<vscale x 1 x i1> %v) {
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; CHECK-LABEL: vreduce_umax_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.umax.nxv1i1(<vscale x 1 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_smax_nxv1i1(<vscale x 1 x i1> %v) {
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; CHECK-LABEL: vreduce_smax_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.smax.nxv1i1(<vscale x 1 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_umin_nxv1i1(<vscale x 1 x i1> %v) {
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; CHECK-LABEL: vreduce_umin_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.umin.nxv1i1(<vscale x 1 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_smin_nxv1i1(<vscale x 1 x i1> %v) {
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; CHECK-LABEL: vreduce_smin_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.smin.nxv1i1(<vscale x 1 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_or_nxv2i1(<vscale x 2 x i1> %v) {
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; CHECK-LABEL: vreduce_or_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_xor_nxv2i1(<vscale x 2 x i1> %v) {
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; CHECK-LABEL: vreduce_xor_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) {
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; CHECK-LABEL: vreduce_and_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_umax_nxv2i1(<vscale x 2 x i1> %v) {
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; CHECK-LABEL: vreduce_umax_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_smax_nxv2i1(<vscale x 2 x i1> %v) {
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; CHECK-LABEL: vreduce_smax_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_umin_nxv2i1(<vscale x 2 x i1> %v) {
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; CHECK-LABEL: vreduce_umin_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_smin_nxv2i1(<vscale x 2 x i1> %v) {
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; CHECK-LABEL: vreduce_smin_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_or_nxv4i1(<vscale x 4 x i1> %v) {
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; CHECK-LABEL: vreduce_or_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_xor_nxv4i1(<vscale x 4 x i1> %v) {
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; CHECK-LABEL: vreduce_xor_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.xor.nxv4i1(<vscale x 4 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) {
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; CHECK-LABEL: vreduce_and_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_umax_nxv4i1(<vscale x 4 x i1> %v) {
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; CHECK-LABEL: vreduce_umax_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.umax.nxv4i1(<vscale x 4 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_smax_nxv4i1(<vscale x 4 x i1> %v) {
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; CHECK-LABEL: vreduce_smax_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.smax.nxv4i1(<vscale x 4 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_umin_nxv4i1(<vscale x 4 x i1> %v) {
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; CHECK-LABEL: vreduce_umin_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.umin.nxv4i1(<vscale x 4 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_smin_nxv4i1(<vscale x 4 x i1> %v) {
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; CHECK-LABEL: vreduce_smin_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.smin.nxv4i1(<vscale x 4 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_or_nxv8i1(<vscale x 8 x i1> %v) {
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; CHECK-LABEL: vreduce_or_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.or.nxv8i1(<vscale x 8 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_xor_nxv8i1(<vscale x 8 x i1> %v) {
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; CHECK-LABEL: vreduce_xor_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.xor.nxv8i1(<vscale x 8 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) {
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; CHECK-LABEL: vreduce_and_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_umax_nxv8i1(<vscale x 8 x i1> %v) {
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; CHECK-LABEL: vreduce_umax_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.umax.nxv8i1(<vscale x 8 x i1> %v)
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ret i1 %red
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}
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define zeroext i1 @vreduce_smax_nxv8i1(<vscale x 8 x i1> %v) {
|
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; CHECK-LABEL: vreduce_smax_nxv8i1:
|
|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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|
; CHECK-NEXT: vmnot.m v8, v0
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%red = call i1 @llvm.vector.reduce.smax.nxv8i1(<vscale x 8 x i1> %v)
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ret i1 %red
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|
}
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|
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define zeroext i1 @vreduce_umin_nxv8i1(<vscale x 8 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umin_nxv8i1:
|
|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
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|
%red = call i1 @llvm.vector.reduce.umin.nxv8i1(<vscale x 8 x i1> %v)
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|
ret i1 %red
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|
}
|
|
|
|
define zeroext i1 @vreduce_smin_nxv8i1(<vscale x 8 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smin_nxv8i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
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|
%red = call i1 @llvm.vector.reduce.smin.nxv8i1(<vscale x 8 x i1> %v)
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|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_or_nxv16i1(<vscale x 16 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_or_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
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|
%red = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %v)
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|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_xor_nxv16i1(<vscale x 16 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_xor_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.xor.nxv16i1(<vscale x 16 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_and_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umax_nxv16i1(<vscale x 16 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umax_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umax.nxv16i1(<vscale x 16 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smax_nxv16i1(<vscale x 16 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smax_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smax.nxv16i1(<vscale x 16 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umin_nxv16i1(<vscale x 16 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umin_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umin.nxv16i1(<vscale x 16 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smin_nxv16i1(<vscale x 16 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smin_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smin.nxv16i1(<vscale x 16 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_or_nxv32i1(<vscale x 32 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_or_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_xor_nxv32i1(<vscale x 32 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_xor_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_and_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umax_nxv32i1(<vscale x 32 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umax_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smax_nxv32i1(<vscale x 32 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smax_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umin_nxv32i1(<vscale x 32 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umin_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smin_nxv32i1(<vscale x 32 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smin_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_or_nxv64i1(<vscale x 64 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_or_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.or.nxv64i1(<vscale x 64 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_xor_nxv64i1(<vscale x 64 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_xor_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.xor.nxv64i1(<vscale x 64 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_and_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umax_nxv64i1(<vscale x 64 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umax_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umax.nxv64i1(<vscale x 64 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smax_nxv64i1(<vscale x 64 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smax_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smax.nxv64i1(<vscale x 64 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umin_nxv64i1(<vscale x 64 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umin_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmnot.m v8, v0
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umin.nxv64i1(<vscale x 64 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smin_nxv64i1(<vscale x 64 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smin_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smin.nxv64i1(<vscale x 64 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_add_nxv1i1(<vscale x 1 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_add_nxv1i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_add_nxv2i1(<vscale x 2 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_add_nxv2i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_add_nxv4i1(<vscale x 4 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_add_nxv4i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_add_nxv8i1(<vscale x 8 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_add_nxv8i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_add_nxv16i1(<vscale x 16 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_add_nxv16i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_add_nxv32i1(<vscale x 32 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_add_nxv32i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_add_nxv64i1(<vscale x 64 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_add_nxv64i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vcpop.m a0, v0
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_or_nxv128i1(<vscale x 128 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_or_nxv128i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v8, v0, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.or.nxv128i1(<vscale x 128 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_xor_nxv128i1(<vscale x 128 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_xor_nxv128i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v8, v0, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.xor.nxv128i1(<vscale x 128 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_and_nxv128i1(<vscale x 128 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_and_nxv128i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmnand.mm v8, v0, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.and.nxv128i1(<vscale x 128 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umax_nxv128i1(<vscale x 128 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umax_nxv128i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v8, v0, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umax.nxv128i1(<vscale x 128 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smax_nxv128i1(<vscale x 128 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smax_nxv128i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmnand.mm v8, v0, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smax.nxv128i1(<vscale x 128 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umin_nxv128i1(<vscale x 128 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umin_nxv128i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmnand.mm v8, v0, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umin.nxv128i1(<vscale x 128 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smin_nxv128i1(<vscale x 128 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smin_nxv128i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v8, v0, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smin.nxv128i1(<vscale x 128 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_or_nxv256i1(<vscale x 256 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_or_nxv256i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v0, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.or.nxv256i1(<vscale x 256 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_xor_nxv256i1(<vscale x 256 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_xor_nxv256i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmxor.mm v9, v0, v9
|
|
; CHECK-NEXT: vmxor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.xor.nxv256i1(<vscale x 256 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_and_nxv256i1(<vscale x 256 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_and_nxv256i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v0, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.and.nxv256i1(<vscale x 256 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umax_nxv256i1(<vscale x 256 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umax_nxv256i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v0, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umax.nxv256i1(<vscale x 256 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smax_nxv256i1(<vscale x 256 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smax_nxv256i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v0, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smax.nxv256i1(<vscale x 256 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umin_nxv256i1(<vscale x 256 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umin_nxv256i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v0, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umin.nxv256i1(<vscale x 256 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smin_nxv256i1(<vscale x 256 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smin_nxv256i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v0, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smin.nxv256i1(<vscale x 256 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_or_nxv512i1(<vscale x 512 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_or_nxv512i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v10, v10, v14
|
|
; CHECK-NEXT: vmor.mm v8, v8, v12
|
|
; CHECK-NEXT: vmor.mm v9, v9, v13
|
|
; CHECK-NEXT: vmor.mm v11, v0, v11
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v11, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.or.nxv512i1(<vscale x 512 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_xor_nxv512i1(<vscale x 512 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_xor_nxv512i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v10, v10, v14
|
|
; CHECK-NEXT: vmxor.mm v8, v8, v12
|
|
; CHECK-NEXT: vmxor.mm v9, v9, v13
|
|
; CHECK-NEXT: vmxor.mm v11, v0, v11
|
|
; CHECK-NEXT: vmxor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmxor.mm v9, v11, v9
|
|
; CHECK-NEXT: vmxor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.xor.nxv512i1(<vscale x 512 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_and_nxv512i1(<vscale x 512 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_and_nxv512i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v10, v10, v14
|
|
; CHECK-NEXT: vmand.mm v8, v8, v12
|
|
; CHECK-NEXT: vmand.mm v9, v9, v13
|
|
; CHECK-NEXT: vmand.mm v11, v0, v11
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v11, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.and.nxv512i1(<vscale x 512 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umax_nxv512i1(<vscale x 512 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umax_nxv512i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v10, v10, v14
|
|
; CHECK-NEXT: vmor.mm v8, v8, v12
|
|
; CHECK-NEXT: vmor.mm v9, v9, v13
|
|
; CHECK-NEXT: vmor.mm v11, v0, v11
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v11, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umax.nxv512i1(<vscale x 512 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smax_nxv512i1(<vscale x 512 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smax_nxv512i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v10, v10, v14
|
|
; CHECK-NEXT: vmand.mm v8, v8, v12
|
|
; CHECK-NEXT: vmand.mm v9, v9, v13
|
|
; CHECK-NEXT: vmand.mm v11, v0, v11
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v11, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smax.nxv512i1(<vscale x 512 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umin_nxv512i1(<vscale x 512 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umin_nxv512i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v10, v10, v14
|
|
; CHECK-NEXT: vmand.mm v8, v8, v12
|
|
; CHECK-NEXT: vmand.mm v9, v9, v13
|
|
; CHECK-NEXT: vmand.mm v11, v0, v11
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v11, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umin.nxv512i1(<vscale x 512 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smin_nxv512i1(<vscale x 512 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smin_nxv512i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v10, v10, v14
|
|
; CHECK-NEXT: vmor.mm v8, v8, v12
|
|
; CHECK-NEXT: vmor.mm v9, v9, v13
|
|
; CHECK-NEXT: vmor.mm v11, v0, v11
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v11, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smin.nxv512i1(<vscale x 512 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_or_nxv1024i1(<vscale x 1024 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_or_nxv1024i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v14, v14, v22
|
|
; CHECK-NEXT: vmor.mm v10, v10, v18
|
|
; CHECK-NEXT: vmor.mm v12, v12, v20
|
|
; CHECK-NEXT: vmor.mm v8, v8, v16
|
|
; CHECK-NEXT: vmor.mm v13, v13, v21
|
|
; CHECK-NEXT: vmor.mm v9, v9, v17
|
|
; CHECK-NEXT: vmor.mm v11, v11, v19
|
|
; CHECK-NEXT: vmor.mm v15, v0, v15
|
|
; CHECK-NEXT: vmor.mm v10, v10, v14
|
|
; CHECK-NEXT: vmor.mm v8, v8, v12
|
|
; CHECK-NEXT: vmor.mm v9, v9, v13
|
|
; CHECK-NEXT: vmor.mm v11, v15, v11
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v11, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.or.nxv1024i1(<vscale x 1024 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_xor_nxv1024i1(<vscale x 1024 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_xor_nxv1024i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmxor.mm v14, v14, v22
|
|
; CHECK-NEXT: vmxor.mm v10, v10, v18
|
|
; CHECK-NEXT: vmxor.mm v12, v12, v20
|
|
; CHECK-NEXT: vmxor.mm v8, v8, v16
|
|
; CHECK-NEXT: vmxor.mm v13, v13, v21
|
|
; CHECK-NEXT: vmxor.mm v9, v9, v17
|
|
; CHECK-NEXT: vmxor.mm v11, v11, v19
|
|
; CHECK-NEXT: vmxor.mm v15, v0, v15
|
|
; CHECK-NEXT: vmxor.mm v10, v10, v14
|
|
; CHECK-NEXT: vmxor.mm v8, v8, v12
|
|
; CHECK-NEXT: vmxor.mm v9, v9, v13
|
|
; CHECK-NEXT: vmxor.mm v11, v15, v11
|
|
; CHECK-NEXT: vmxor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmxor.mm v9, v11, v9
|
|
; CHECK-NEXT: vmxor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: andi a0, a0, 1
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.xor.nxv1024i1(<vscale x 1024 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_and_nxv1024i1(<vscale x 1024 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_and_nxv1024i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v14, v14, v22
|
|
; CHECK-NEXT: vmand.mm v10, v10, v18
|
|
; CHECK-NEXT: vmand.mm v12, v12, v20
|
|
; CHECK-NEXT: vmand.mm v8, v8, v16
|
|
; CHECK-NEXT: vmand.mm v13, v13, v21
|
|
; CHECK-NEXT: vmand.mm v9, v9, v17
|
|
; CHECK-NEXT: vmand.mm v11, v11, v19
|
|
; CHECK-NEXT: vmand.mm v15, v0, v15
|
|
; CHECK-NEXT: vmand.mm v10, v10, v14
|
|
; CHECK-NEXT: vmand.mm v8, v8, v12
|
|
; CHECK-NEXT: vmand.mm v9, v9, v13
|
|
; CHECK-NEXT: vmand.mm v11, v15, v11
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v11, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.and.nxv1024i1(<vscale x 1024 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umax_nxv1024i1(<vscale x 1024 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umax_nxv1024i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v14, v14, v22
|
|
; CHECK-NEXT: vmor.mm v10, v10, v18
|
|
; CHECK-NEXT: vmor.mm v12, v12, v20
|
|
; CHECK-NEXT: vmor.mm v8, v8, v16
|
|
; CHECK-NEXT: vmor.mm v13, v13, v21
|
|
; CHECK-NEXT: vmor.mm v9, v9, v17
|
|
; CHECK-NEXT: vmor.mm v11, v11, v19
|
|
; CHECK-NEXT: vmor.mm v15, v0, v15
|
|
; CHECK-NEXT: vmor.mm v10, v10, v14
|
|
; CHECK-NEXT: vmor.mm v8, v8, v12
|
|
; CHECK-NEXT: vmor.mm v9, v9, v13
|
|
; CHECK-NEXT: vmor.mm v11, v15, v11
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v11, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umax.nxv1024i1(<vscale x 1024 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smax_nxv1024i1(<vscale x 1024 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smax_nxv1024i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v14, v14, v22
|
|
; CHECK-NEXT: vmand.mm v10, v10, v18
|
|
; CHECK-NEXT: vmand.mm v12, v12, v20
|
|
; CHECK-NEXT: vmand.mm v8, v8, v16
|
|
; CHECK-NEXT: vmand.mm v13, v13, v21
|
|
; CHECK-NEXT: vmand.mm v9, v9, v17
|
|
; CHECK-NEXT: vmand.mm v11, v11, v19
|
|
; CHECK-NEXT: vmand.mm v15, v0, v15
|
|
; CHECK-NEXT: vmand.mm v10, v10, v14
|
|
; CHECK-NEXT: vmand.mm v8, v8, v12
|
|
; CHECK-NEXT: vmand.mm v9, v9, v13
|
|
; CHECK-NEXT: vmand.mm v11, v15, v11
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v11, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smax.nxv1024i1(<vscale x 1024 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_umin_nxv1024i1(<vscale x 1024 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_umin_nxv1024i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmand.mm v14, v14, v22
|
|
; CHECK-NEXT: vmand.mm v10, v10, v18
|
|
; CHECK-NEXT: vmand.mm v12, v12, v20
|
|
; CHECK-NEXT: vmand.mm v8, v8, v16
|
|
; CHECK-NEXT: vmand.mm v13, v13, v21
|
|
; CHECK-NEXT: vmand.mm v9, v9, v17
|
|
; CHECK-NEXT: vmand.mm v11, v11, v19
|
|
; CHECK-NEXT: vmand.mm v15, v0, v15
|
|
; CHECK-NEXT: vmand.mm v10, v10, v14
|
|
; CHECK-NEXT: vmand.mm v8, v8, v12
|
|
; CHECK-NEXT: vmand.mm v9, v9, v13
|
|
; CHECK-NEXT: vmand.mm v11, v15, v11
|
|
; CHECK-NEXT: vmand.mm v8, v8, v10
|
|
; CHECK-NEXT: vmand.mm v9, v11, v9
|
|
; CHECK-NEXT: vmnand.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: seqz a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.umin.nxv1024i1(<vscale x 1024 x i1> %v)
|
|
ret i1 %red
|
|
}
|
|
|
|
define zeroext i1 @vreduce_smin_nxv1024i1(<vscale x 1024 x i1> %v) {
|
|
; CHECK-LABEL: vreduce_smin_nxv1024i1:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
|
|
; CHECK-NEXT: vmor.mm v14, v14, v22
|
|
; CHECK-NEXT: vmor.mm v10, v10, v18
|
|
; CHECK-NEXT: vmor.mm v12, v12, v20
|
|
; CHECK-NEXT: vmor.mm v8, v8, v16
|
|
; CHECK-NEXT: vmor.mm v13, v13, v21
|
|
; CHECK-NEXT: vmor.mm v9, v9, v17
|
|
; CHECK-NEXT: vmor.mm v11, v11, v19
|
|
; CHECK-NEXT: vmor.mm v15, v0, v15
|
|
; CHECK-NEXT: vmor.mm v10, v10, v14
|
|
; CHECK-NEXT: vmor.mm v8, v8, v12
|
|
; CHECK-NEXT: vmor.mm v9, v9, v13
|
|
; CHECK-NEXT: vmor.mm v11, v15, v11
|
|
; CHECK-NEXT: vmor.mm v8, v8, v10
|
|
; CHECK-NEXT: vmor.mm v9, v11, v9
|
|
; CHECK-NEXT: vmor.mm v8, v9, v8
|
|
; CHECK-NEXT: vcpop.m a0, v8
|
|
; CHECK-NEXT: snez a0, a0
|
|
; CHECK-NEXT: ret
|
|
%red = call i1 @llvm.vector.reduce.smin.nxv1024i1(<vscale x 1024 x i1> %v)
|
|
ret i1 %red
|
|
}
|