derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
65 lines
3.1 KiB
LLVM
65 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix NOSUBREG
|
|
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -enable-subreg-liveness=true | FileCheck %s --check-prefix SUBREG
|
|
|
|
; This test checks that vrgatherei16 instructions are correctly
|
|
; register-allocated. The LMUL=1 destination register groups may not overlap
|
|
; with the EMUL=2 source vector register groups.
|
|
|
|
; FIXME: enabling subregister liveness results in incorrect register
|
|
; allocation!
|
|
|
|
define internal void @foo(<vscale x 1 x i16> %v15, <vscale x 1 x i16> %0, <vscale x 1 x i16> %vs12.i.i.i, <vscale x 1 x i16> %1, <vscale x 8 x i8> %v37) {
|
|
; NOSUBREG-LABEL: foo:
|
|
; NOSUBREG: # %bb.0: # %loopIR.preheader.i.i
|
|
; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; NOSUBREG-NEXT: vmv.v.i v9, 0
|
|
; NOSUBREG-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; NOSUBREG-NEXT: vmv.v.i v14, 0
|
|
; NOSUBREG-NEXT: vmv1r.v v8, v9
|
|
; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma
|
|
; NOSUBREG-NEXT: vrgatherei16.vv v8, v9, v14
|
|
; NOSUBREG-NEXT: .LBB0_1: # %loopIR3.i.i
|
|
; NOSUBREG-NEXT: # =>This Inner Loop Header: Depth=1
|
|
; NOSUBREG-NEXT: vl1r.v v9, (zero)
|
|
; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma
|
|
; NOSUBREG-NEXT: vmv1r.v v13, v12
|
|
; NOSUBREG-NEXT: vrgatherei16.vv v13, v9, v10
|
|
; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; NOSUBREG-NEXT: vand.vv v9, v8, v13
|
|
; NOSUBREG-NEXT: vs1r.v v9, (zero)
|
|
; NOSUBREG-NEXT: j .LBB0_1
|
|
;
|
|
; SUBREG-LABEL: foo:
|
|
; SUBREG: # %bb.0: # %loopIR.preheader.i.i
|
|
; SUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; SUBREG-NEXT: vmv.v.i v9, 0
|
|
; SUBREG-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; SUBREG-NEXT: vmv.v.i v14, 0
|
|
; SUBREG-NEXT: vmv1r.v v8, v9
|
|
; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma
|
|
; SUBREG-NEXT: vrgatherei16.vv v8, v9, v14
|
|
; SUBREG-NEXT: .LBB0_1: # %loopIR3.i.i
|
|
; SUBREG-NEXT: # =>This Inner Loop Header: Depth=1
|
|
; SUBREG-NEXT: vl1r.v v9, (zero)
|
|
; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma
|
|
; SUBREG-NEXT: vmv1r.v v13, v12
|
|
; SUBREG-NEXT: vrgatherei16.vv v13, v9, v10
|
|
; SUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma
|
|
; SUBREG-NEXT: vand.vv v9, v8, v13
|
|
; SUBREG-NEXT: vs1r.v v9, (zero)
|
|
; SUBREG-NEXT: j .LBB0_1
|
|
loopIR.preheader.i.i:
|
|
%v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)
|
|
br label %loopIR3.i.i
|
|
|
|
loopIR3.i.i: ; preds = %loopIR3.i.i, %loopIR.preheader.i.i
|
|
%v376 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 8
|
|
%v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i16> zeroinitializer, i64 4)
|
|
%v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> %v37, <vscale x 8 x i8> %v376, <vscale x 8 x i16> %v18, i64 4)
|
|
%v42 = and <vscale x 8 x i8> %v38, %v40
|
|
store <vscale x 8 x i8> %v42, ptr addrspace(1) null, align 4
|
|
br label %loopIR3.i.i
|
|
}
|
|
|