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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-coalesce.mir
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derek.holloway 7502bf64a4
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=liveintervals,riscv-insert-vsetvli %s -o - | FileCheck %s
---
name: coalesce
tracksRegLiveness: true
noPhis: true
body: |
; CHECK-LABEL: name: coalesce
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:gprnox0 = IMPLICIT_DEF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v10m2 = PseudoVMV_V_I_M2 undef renamable $v10m2, 0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x04000000), %bb.2(0x7c000000)
; CHECK-NEXT: liveins: $v10m2, $v12m2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BEQ undef %2:gpr, $x0, %bb.2
; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000)
; CHECK-NEXT: liveins: $v8m2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x0 = PseudoVSETVLI [[DEF]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v10 = PseudoVMV_S_X undef renamable $v10, undef %2:gpr, $noreg /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: dead renamable $v8 = PseudoVREDSUM_VS_M2_E32 undef renamable $v8, killed undef renamable $v8m2, killed undef renamable $v10, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: BNE undef %3:gpr, $x0, %bb.1
; CHECK-NEXT: PseudoBR %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: PseudoRET
bb.0:
successors: %bb.1(0x80000000)
%78:gprnox0 = IMPLICIT_DEF
bb.1:
successors: %bb.2(0x80000000)
%46:gprnox0 = PseudoVSETVLI %78, 199 /* e8, mf2, ta, ma */, implicit-def dead $vl, implicit-def dead $vtype
renamable $v10m2 = PseudoVMV_V_I_M2 undef renamable $v10m2, 0, -1, 5 /* e32 */, 0 /* tu, mu */
bb.2:
successors: %bb.3(0x04000000), %bb.2(0x7c000000)
liveins: $v10m2, $v12m2
BEQ undef %54:gpr, $x0, %bb.2
PseudoBR %bb.3
bb.3:
successors: %bb.1(0x7c000000), %bb.4(0x04000000)
liveins: $v8m2
renamable $v10 = PseudoVMV_S_X undef renamable $v10, undef %54:gpr, %46, 5 /* e32 */
dead renamable $v8 = PseudoVREDSUM_VS_M2_E32 undef renamable $v8, killed undef renamable $v8m2, killed undef renamable $v10, %46, 5 /* e32 */, 0 /* tu, mu */
BNE undef %29:gpr, $x0, %bb.1
PseudoBR %bb.4
bb.4:
PseudoRET
...