derek.holloway
7502bf64a4
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1110 lines
44 KiB
YAML
1110 lines
44 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -verify-machineinstrs \
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# RUN: -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s
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--- |
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source_filename = "vsetvli-insert.ll"
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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define <vscale x 1 x i64> @load_add_or_sub(i8 zeroext %cond, ptr %0, <vscale x 1 x i64> %1, i64 %2) #0 {
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entry:
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%a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, ptr %0, i64 %2)
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%tobool = icmp eq i8 %cond, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
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br label %if.end
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if.else: ; preds = %entry
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%c = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
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ret <vscale x 1 x i64> %d
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}
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define void @load_zext_or_sext(i8 zeroext %cond, ptr %0, ptr %1, i64 %2) #0 {
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entry:
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%a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, ptr %0, i64 %2)
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%tobool = icmp eq i8 %cond, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %2)
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br label %if.end
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if.else: ; preds = %entry
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%c = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %2)
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
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call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> %d, ptr %1, i64 %2)
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ret void
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}
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define i64 @vmv_x_s(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {
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entry:
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%tobool = icmp eq i8 %cond, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)
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br label %if.end
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if.else: ; preds = %entry
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%b = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %1, i64 %2)
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%c = phi <vscale x 1 x i64> [ %a, %if.then ], [ %b, %if.else ]
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%d = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> %c)
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ret i64 %d
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}
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define <vscale x 1 x i64> @vsetvli_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {
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entry:
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%vl = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0)
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%tobool = icmp eq i8 %cond, 0
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br i1 %tobool, label %if.else, label %if.then
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if.then: ; preds = %entry
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%b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %vl)
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br label %if.end
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if.else: ; preds = %entry
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%c = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %vl)
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]
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ret <vscale x 1 x i64> %d
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}
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define void @vsetvli_vcpop() {
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ret void
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}
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define void @vsetvli_loop_store() {
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ret void
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}
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define void @vsetvli_loop_store2() {
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ret void
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}
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define void @redusum_loop(ptr nocapture noundef readonly %a, i32 noundef signext %n, ptr nocapture noundef writeonly %res) #0 {
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entry:
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br label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %a, %entry ]
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%lsr.iv = phi i64 [ %lsr.iv.next, %vector.body ], [ 2048, %entry ]
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%vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %0, %vector.body ]
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%lsr.iv12 = bitcast ptr %lsr.iv1 to ptr
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%wide.load = load <4 x i32>, ptr %lsr.iv12, align 4
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%0 = add <4 x i32> %wide.load, %vec.phi
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%lsr.iv.next = add nsw i64 %lsr.iv, -4
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%scevgep = getelementptr i32, ptr %lsr.iv1, i64 4
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%1 = icmp eq i64 %lsr.iv.next, 0
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br i1 %1, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %0)
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store i32 %2, ptr %res, align 4
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ret void
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}
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define void @vsetvli_vluxei64_regression() {
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ret void
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}
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define void @if_in_loop() {
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ret void
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}
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define void @pre_undemanded_vl() {
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ret void
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}
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define void @clobberred_forwarded_avl() {
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ret void
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}
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define void @clobberred_forwarded_phi_avl() {
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ret void
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}
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define void @avl_is_last_instr() {
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ret void
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}
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attributes #0 = { "target-features"="+v" }
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...
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---
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name: load_add_or_sub
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vr }
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- { id: 1, class: vr }
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- { id: 2, class: vr }
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- { id: 3, class: vr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: vr }
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- { id: 7, class: gprnox0 }
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- { id: 8, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%4' }
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- { reg: '$x11', virtual-reg: '%5' }
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- { reg: '$v8', virtual-reg: '%6' }
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- { reg: '$x12', virtual-reg: '%7' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: load_add_or_sub
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)
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; CHECK-NEXT: liveins: $x10, $x11, $v8, $x12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.if.then:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoBR %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.if.else:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.if.end:
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; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype
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; CHECK-NEXT: PseudoRET implicit $v8
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bb.0.entry:
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successors: %bb.2(0x30000000), %bb.1(0x50000000)
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liveins: $x10, $x11, $v8, $x12
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%7:gprnox0 = COPY $x12
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%6:vr = COPY $v8
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%5:gpr = COPY $x11
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%4:gpr = COPY $x10
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%0:vr = PseudoVLE64_V_M1 undef $noreg, %5, %7, 6, 0
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%8:gpr = COPY $x0
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BEQ %4, %8, %bb.2
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PseudoBR %bb.1
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bb.1.if.then:
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%1:vr = PseudoVADD_VV_M1 undef $noreg, %0, %6, %7, 6, 0
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PseudoBR %bb.3
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bb.2.if.else:
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%2:vr = PseudoVSUB_VV_M1 undef $noreg, %0, %6, %7, 6, 0
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bb.3.if.end:
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%3:vr = PHI %1, %bb.1, %2, %bb.2
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$v8 = COPY %3
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PseudoRET implicit $v8
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...
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---
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name: load_zext_or_sext
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vr }
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- { id: 1, class: vr }
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- { id: 2, class: vr }
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- { id: 3, class: vr }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: gpr }
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- { id: 7, class: gprnox0 }
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- { id: 8, class: gpr }
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liveins:
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- { reg: '$x10', virtual-reg: '%4' }
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- { reg: '$x11', virtual-reg: '%5' }
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- { reg: '$x12', virtual-reg: '%6' }
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- { reg: '$x13', virtual-reg: '%7' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: load_zext_or_sext
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY2]], $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.if.then:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
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; CHECK-NEXT: early-clobber %9:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoBR %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.if.else:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
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; CHECK-NEXT: early-clobber %9:vr = PseudoVSEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.if.end:
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; CHECK-NEXT: PseudoVSE64_V_M1 %9, [[COPY1]], $noreg /* vl */, 6 /* e64 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoRET
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bb.0.entry:
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successors: %bb.2(0x30000000), %bb.1(0x50000000)
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liveins: $x10, $x11, $x12, $x13
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%7:gprnox0 = COPY $x13
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%6:gpr = COPY $x12
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%5:gpr = COPY $x11
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%4:gpr = COPY $x10
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%0:vr = PseudoVLE32_V_MF2 undef $noreg, %5, %7, 5, 0
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%8:gpr = COPY $x0
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BEQ %4, %8, %bb.2
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PseudoBR %bb.1
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bb.1.if.then:
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early-clobber %1:vr = PseudoVZEXT_VF2_M1 undef $noreg, %0, %7, 6, 0
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PseudoBR %bb.3
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bb.2.if.else:
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early-clobber %2:vr = PseudoVSEXT_VF2_M1 undef $noreg, %0, %7, 6, 0
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bb.3.if.end:
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%3:vr = PHI %1, %bb.1, %2, %bb.2
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PseudoVSE64_V_M1 %3, %6, %7, 6
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PseudoRET
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|
|
|
...
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|
---
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|
name: vmv_x_s
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alignment: 4
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|
tracksRegLiveness: true
|
|
registers:
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- { id: 0, class: vr }
|
|
- { id: 1, class: vr }
|
|
- { id: 2, class: vr }
|
|
- { id: 3, class: gpr }
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|
- { id: 4, class: vr }
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|
- { id: 5, class: vr }
|
|
- { id: 6, class: gprnox0 }
|
|
- { id: 7, class: gpr }
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|
- { id: 8, class: gpr }
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liveins:
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|
- { reg: '$x10', virtual-reg: '%3' }
|
|
- { reg: '$v8', virtual-reg: '%4' }
|
|
- { reg: '$v9', virtual-reg: '%5' }
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|
- { reg: '$x11', virtual-reg: '%6' }
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|
frameInfo:
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|
maxAlignment: 1
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
; CHECK-LABEL: name: vmv_x_s
|
|
; CHECK: bb.0.entry:
|
|
; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
|
; CHECK-NEXT: liveins: $x10, $v8, $v9, $x11
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2
|
|
; CHECK-NEXT: PseudoBR %bb.1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1.if.then:
|
|
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoBR %bb.3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2.if.else:
|
|
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY1]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.3.if.end:
|
|
; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVADD_VV_M1_]], 6 /* e64 */, implicit $vtype
|
|
; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]
|
|
; CHECK-NEXT: PseudoRET implicit $x10
|
|
bb.0.entry:
|
|
successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
|
liveins: $x10, $v8, $v9, $x11
|
|
|
|
%6:gprnox0 = COPY $x11
|
|
%5:vr = COPY $v9
|
|
%4:vr = COPY $v8
|
|
%3:gpr = COPY $x10
|
|
%7:gpr = COPY $x0
|
|
BEQ %3, %7, %bb.2
|
|
PseudoBR %bb.1
|
|
|
|
bb.1.if.then:
|
|
%0:vr = PseudoVADD_VV_M1 undef $noreg, %4, %5, %6, 6, 0
|
|
PseudoBR %bb.3
|
|
|
|
bb.2.if.else:
|
|
%1:vr = PseudoVSUB_VV_M1 undef $noreg, %5, %5, %6, 6, 0
|
|
|
|
bb.3.if.end:
|
|
%2:vr = PHI %0, %bb.1, %1, %bb.2
|
|
%8:gpr = PseudoVMV_X_S %2, 6
|
|
$x10 = COPY %8
|
|
PseudoRET implicit $x10
|
|
|
|
...
|
|
---
|
|
name: vsetvli_add_or_sub
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gprnox0 }
|
|
- { id: 1, class: vr }
|
|
- { id: 2, class: vr }
|
|
- { id: 3, class: vr }
|
|
- { id: 4, class: gpr }
|
|
- { id: 5, class: vr }
|
|
- { id: 6, class: vr }
|
|
- { id: 7, class: gprnox0 }
|
|
- { id: 8, class: gpr }
|
|
liveins:
|
|
- { reg: '$x10', virtual-reg: '%4' }
|
|
- { reg: '$v8', virtual-reg: '%5' }
|
|
- { reg: '$v9', virtual-reg: '%6' }
|
|
- { reg: '$x11', virtual-reg: '%7' }
|
|
frameInfo:
|
|
maxAlignment: 1
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
; CHECK-LABEL: name: vsetvli_add_or_sub
|
|
; CHECK: bb.0.entry:
|
|
; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
|
; CHECK-NEXT: liveins: $x10, $v8, $v9, $x11
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2
|
|
; CHECK-NEXT: PseudoBR %bb.1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1.if.then:
|
|
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoBR %bb.3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2.if.else:
|
|
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg /* vl */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.3.if.end:
|
|
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype
|
|
; CHECK-NEXT: PseudoRET implicit $v8
|
|
bb.0.entry:
|
|
successors: %bb.2(0x30000000), %bb.1(0x50000000)
|
|
liveins: $x10, $v8, $v9, $x11
|
|
|
|
%7:gprnox0 = COPY $x11
|
|
%6:vr = COPY $v9
|
|
%5:vr = COPY $v8
|
|
%4:gpr = COPY $x10
|
|
%0:gprnox0 = PseudoVSETVLI %7, 88, implicit-def dead $vl, implicit-def dead $vtype
|
|
%8:gpr = COPY $x0
|
|
BEQ %4, %8, %bb.2
|
|
PseudoBR %bb.1
|
|
|
|
bb.1.if.then:
|
|
%1:vr = PseudoVADD_VV_M1 undef $noreg, %5, %6, %0, 6, 0
|
|
PseudoBR %bb.3
|
|
|
|
bb.2.if.else:
|
|
%2:vr = PseudoVSUB_VV_M1 undef $noreg, %5, %6, %0, 6, 0
|
|
|
|
bb.3.if.end:
|
|
%3:vr = PHI %1, %bb.1, %2, %bb.2
|
|
$v8 = COPY %3
|
|
PseudoRET implicit $v8
|
|
|
|
...
|
|
---
|
|
name: vsetvli_vcpop
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
- { id: 3, class: vr, preferred-register: '' }
|
|
- { id: 4, class: vrnov0, preferred-register: '' }
|
|
- { id: 5, class: vmv0, preferred-register: '' }
|
|
- { id: 6, class: vrnov0, preferred-register: '' }
|
|
- { id: 7, class: gpr, preferred-register: '' }
|
|
- { id: 8, class: gpr, preferred-register: '' }
|
|
- { id: 9, class: gpr, preferred-register: '' }
|
|
- { id: 10, class: gpr, preferred-register: '' }
|
|
- { id: 11, class: vr, preferred-register: '' }
|
|
body: |
|
|
; CHECK-LABEL: name: vsetvli_vcpop
|
|
; CHECK: bb.0:
|
|
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
|
; CHECK-NEXT: liveins: $x10, $x11
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 undef $noreg, 0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1:
|
|
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 [[PseudoVID_V_MF2_]], 0, -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]], implicit $vtype
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
|
|
; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY]], $v0, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
|
|
; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSEQ_VI_MF2_]], -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF
|
|
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3
|
|
; CHECK-NEXT: PseudoBR %bb.2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2:
|
|
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = LWU [[COPY1]], 0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.3:
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
|
|
; CHECK-NEXT: [[PseudoVADD_VX_MF2_:%[0-9]+]]:vr = nsw PseudoVADD_VX_MF2 undef $noreg, [[PseudoVLE32_V_MF2_MASK]], [[DEF]], -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: $v0 = COPY [[PseudoVADD_VX_MF2_]], implicit $vtype
|
|
; CHECK-NEXT: PseudoRET implicit $v0
|
|
bb.0:
|
|
successors: %bb.1(0x80000000)
|
|
liveins: $x10, $x11
|
|
|
|
%0:gpr = COPY $x11
|
|
%1:gpr = COPY $x10
|
|
%2:gpr = IMPLICIT_DEF
|
|
%3:vr = PseudoVID_V_MF2 undef $noreg, -1, 6, 0
|
|
%4:vrnov0 = PseudoVMV_V_I_MF2 undef $noreg, 0, -1, 5, 0
|
|
|
|
bb.1:
|
|
successors: %bb.2(0x40000000), %bb.3(0x40000000)
|
|
|
|
%5:vmv0 = PseudoVMSEQ_VI_MF2 killed %3, 0, -1, 5
|
|
$v0 = COPY %5
|
|
%6:vrnov0 = PseudoVLE32_V_MF2_MASK %4, killed %0, $v0, -1, 5, 0
|
|
%7:gpr = PseudoVCPOP_M_B64 %5, -1, 0
|
|
%8:gpr = COPY $x0
|
|
BEQ killed %7, %8, %bb.3
|
|
PseudoBR %bb.2
|
|
|
|
bb.2:
|
|
successors: %bb.3(0x80000000)
|
|
|
|
%9:gpr = LWU %1, 0
|
|
|
|
bb.3:
|
|
%10:gpr = PHI %2, %bb.1, %9, %bb.2
|
|
%11:vr = nsw PseudoVADD_VX_MF2 undef $noreg, %6, %10, -1, 5, 0
|
|
$v0 = COPY %11
|
|
PseudoRET implicit $v0
|
|
...
|
|
---
|
|
name: vsetvli_loop_store
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
- { id: 3, class: gpr, preferred-register: '' }
|
|
- { id: 4, class: vr, preferred-register: '' }
|
|
- { id: 5, class: gpr, preferred-register: '' }
|
|
- { id: 6, class: gpr, preferred-register: '' }
|
|
- { id: 7, class: vr, preferred-register: '' }
|
|
- { id: 8, class: gpr, preferred-register: '' }
|
|
- { id: 9, class: gpr, preferred-register: '' }
|
|
- { id: 10, class: gpr, preferred-register: '' }
|
|
body: |
|
|
; CHECK-LABEL: name: vsetvli_loop_store
|
|
; CHECK: bb.0:
|
|
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
|
; CHECK-NEXT: liveins: $x10, $x11
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
|
|
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
|
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1:
|
|
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY2]], [[SRLI]]
|
|
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]
|
|
; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = ADDI [[COPY2]], 1
|
|
; CHECK-NEXT: BLTU [[COPY2]], [[COPY1]], %bb.1
|
|
; CHECK-NEXT: PseudoBR %bb.2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2:
|
|
; CHECK-NEXT: PseudoRET
|
|
bb.0:
|
|
liveins: $x10, $x11
|
|
%0:gpr = COPY $x10
|
|
%1:gpr = PseudoReadVLENB
|
|
%2:gpr = SRLI %1:gpr, 3
|
|
%3:gpr = COPY $x11
|
|
%4:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 0
|
|
%5:gpr = COPY $x0
|
|
|
|
bb.1:
|
|
successors: %bb.1, %bb.2
|
|
|
|
%6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.1
|
|
%7:vr = PseudoVADD_VX_M1 undef $noreg, %4:vr, %6:gpr, -1, 6, 0
|
|
%8:gpr = MUL %6:gpr, %2:gpr
|
|
%9:gpr = ADD %0:gpr, %8:gpr
|
|
PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5
|
|
%10:gpr = ADDI %6:gpr, 1
|
|
BLTU %10:gpr, %3:gpr, %bb.1
|
|
PseudoBR %bb.2
|
|
|
|
bb.2:
|
|
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: vsetvli_loop_store2
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr, preferred-register: '' }
|
|
- { id: 1, class: gpr, preferred-register: '' }
|
|
- { id: 2, class: gpr, preferred-register: '' }
|
|
- { id: 3, class: gpr, preferred-register: '' }
|
|
- { id: 4, class: vr, preferred-register: '' }
|
|
- { id: 5, class: gpr, preferred-register: '' }
|
|
- { id: 6, class: gpr, preferred-register: '' }
|
|
- { id: 7, class: vr, preferred-register: '' }
|
|
- { id: 8, class: gpr, preferred-register: '' }
|
|
- { id: 9, class: gpr, preferred-register: '' }
|
|
- { id: 10, class: gpr, preferred-register: '' }
|
|
body: |
|
|
; CHECK-LABEL: name: vsetvli_loop_store2
|
|
; CHECK: bb.0:
|
|
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
|
; CHECK-NEXT: liveins: $x10, $x11
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB
|
|
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
|
|
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1:
|
|
; CHECK-NEXT: successors: %bb.2(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY2]], [[SRLI]]
|
|
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]
|
|
; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1 /* vl=VLMAX */, 5 /* e32 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = ADDI [[COPY2]], 1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2:
|
|
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: BLTU [[COPY2]], [[COPY1]], %bb.1
|
|
; CHECK-NEXT: PseudoBR %bb.3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.3:
|
|
; CHECK-NEXT: PseudoRET
|
|
bb.0:
|
|
liveins: $x10, $x11
|
|
%0:gpr = COPY $x10
|
|
%1:gpr = PseudoReadVLENB
|
|
%2:gpr = SRLI %1:gpr, 3
|
|
%3:gpr = COPY $x11
|
|
%4:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 3
|
|
%5:gpr = COPY $x0
|
|
|
|
bb.1:
|
|
successors: %bb.3
|
|
|
|
%6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.3
|
|
%7:vr = PseudoVADD_VX_M1 undef $noreg, %4:vr, %6:gpr, -1, 6, 0
|
|
%8:gpr = MUL %6:gpr, %2:gpr
|
|
%9:gpr = ADD %0:gpr, %8:gpr
|
|
PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5
|
|
%10:gpr = ADDI %6:gpr, 1
|
|
|
|
bb.3:
|
|
successors: %bb.1, %bb.2
|
|
BLTU %10:gpr, %3:gpr, %bb.1
|
|
PseudoBR %bb.2
|
|
|
|
bb.2:
|
|
|
|
PseudoRET
|
|
...
|
|
---
|
|
name: redusum_loop
|
|
alignment: 4
|
|
tracksRegLiveness: true
|
|
registers:
|
|
- { id: 0, class: gpr }
|
|
- { id: 1, class: gpr }
|
|
- { id: 2, class: vr }
|
|
- { id: 3, class: vr }
|
|
- { id: 4, class: gpr }
|
|
- { id: 5, class: gpr }
|
|
- { id: 6, class: gpr }
|
|
- { id: 7, class: gpr }
|
|
- { id: 8, class: gpr }
|
|
- { id: 9, class: gpr }
|
|
- { id: 10, class: vr }
|
|
- { id: 11, class: vr }
|
|
- { id: 12, class: vr }
|
|
- { id: 13, class: gpr }
|
|
- { id: 14, class: vr }
|
|
- { id: 15, class: vr }
|
|
- { id: 16, class: vr }
|
|
- { id: 17, class: vr }
|
|
- { id: 18, class: gpr }
|
|
- { id: 19, class: gpr }
|
|
- { id: 20, class: vr }
|
|
- { id: 21, class: vr }
|
|
- { id: 22, class: vr }
|
|
- { id: 23, class: vr }
|
|
- { id: 24, class: vr }
|
|
liveins:
|
|
- { reg: '$x10', virtual-reg: '%6' }
|
|
- { reg: '$x12', virtual-reg: '%8' }
|
|
frameInfo:
|
|
maxAlignment: 1
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
; CHECK-LABEL: name: redusum_loop
|
|
; CHECK: bb.0.entry:
|
|
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
|
; CHECK-NEXT: liveins: $x10, $x12
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1
|
|
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -2048
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1.vector.body:
|
|
; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 undef $noreg, [[COPY1]], 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4)
|
|
; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE32_V_M1_]], [[PseudoVMV_V_I_M1_]], 4 /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = nsw ADDI [[ADDIW]], -4
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = ADDI [[COPY1]], 16
|
|
; CHECK-NEXT: BNE [[ADDIW]], $x0, %bb.1
|
|
; CHECK-NEXT: PseudoBR %bb.2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2.middle.block:
|
|
; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X undef $noreg, $x0, 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVMV_V_I_M1_]], [[PseudoVMV_S_X]], 4 /* vl */, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: PseudoVSE32_V_M1 [[PseudoVREDSUM_VS_M1_E8_]], [[COPY]], 1 /* vl */, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res)
|
|
; CHECK-NEXT: PseudoRET
|
|
bb.0.entry:
|
|
liveins: $x10, $x12
|
|
|
|
%8:gpr = COPY $x12
|
|
%6:gpr = COPY $x10
|
|
%11:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 4, 5, 0
|
|
%12:vr = COPY %11
|
|
%10:vr = COPY %12
|
|
%13:gpr = LUI 1
|
|
%9:gpr = ADDIW killed %13, -2048
|
|
|
|
bb.1.vector.body:
|
|
successors: %bb.2(0x04000000), %bb.1(0x7c000000)
|
|
|
|
%0:gpr = PHI %6, %bb.0, %5, %bb.1
|
|
%1:gpr = PHI %9, %bb.0, %4, %bb.1
|
|
%2:vr = PHI %10, %bb.0, %16, %bb.1
|
|
%14:vr = PseudoVLE32_V_M1 undef $noreg, %0, 4, 5, 0 :: (load (s128) from %ir.lsr.iv12, align 4)
|
|
%16:vr = PseudoVADD_VV_M1 undef $noreg, killed %14, %2, 4, 5, 0
|
|
%4:gpr = nsw ADDI %1, -4
|
|
%5:gpr = ADDI %0, 16
|
|
%18:gpr = COPY $x0
|
|
BNE %4, %18, %bb.1
|
|
PseudoBR %bb.2
|
|
|
|
bb.2.middle.block:
|
|
%19:gpr = COPY $x0
|
|
%20:vr = PseudoVMV_S_X undef $noreg, %19, 1, 5
|
|
%23:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, %16, killed %20, 4, 5, 1
|
|
PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res)
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: vsetvli_vluxei64_regression
|
|
tracksRegLiveness: true
|
|
body: |
|
|
; CHECK-LABEL: name: vsetvli_vluxei64_regression
|
|
; CHECK: bb.0:
|
|
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
|
; CHECK-NEXT: liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %a:gpr = COPY $x10
|
|
; CHECK-NEXT: %b:gpr = COPY $x11
|
|
; CHECK-NEXT: %inaddr:gpr = COPY $x12
|
|
; CHECK-NEXT: %idxs:vr = COPY $v0
|
|
; CHECK-NEXT: %t1:vr = COPY $v1
|
|
; CHECK-NEXT: %t3:vr = COPY $v2
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vrnov0 = COPY $v3
|
|
; CHECK-NEXT: %t5:vrnov0 = COPY $v1
|
|
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1 /* vl=VLMAX */, 6 /* e64 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoBR %bb.1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1:
|
|
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: BEQ %a, $x0, %bb.3
|
|
; CHECK-NEXT: PseudoBR %bb.2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2:
|
|
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: $v0 = COPY %mask, implicit $vtype
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
|
|
; CHECK-NEXT: early-clobber [[COPY]]:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, %inaddr, %idxs, $v0, -1 /* vl=VLMAX */, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoBR %bb.3
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.3:
|
|
; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: $v0 = COPY %mask, implicit $vtype
|
|
; CHECK-NEXT: PseudoVSOXEI64_V_M1_MF8_MASK [[COPY]], %b, %idxs, $v0, -1 /* vl=VLMAX */, 3 /* e8 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: PseudoRET
|
|
bb.0:
|
|
successors: %bb.1
|
|
liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3
|
|
|
|
%a:gpr = COPY $x10
|
|
%b:gpr = COPY $x11
|
|
%inaddr:gpr = COPY $x12
|
|
%idxs:vr = COPY $v0
|
|
%t1:vr = COPY $v1
|
|
%t3:vr = COPY $v2
|
|
%t4:vr = COPY $v3
|
|
%t5:vrnov0 = COPY $v1
|
|
%t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6
|
|
PseudoBR %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.3, %bb.2
|
|
|
|
%mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1, 0
|
|
%t2:gpr = COPY $x0
|
|
BEQ %a, %t2, %bb.3
|
|
PseudoBR %bb.2
|
|
|
|
bb.2:
|
|
successors: %bb.3
|
|
|
|
$v0 = COPY %mask
|
|
early-clobber %t0:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, killed %inaddr, %idxs, $v0, -1, 3, 1
|
|
%ldval:vr = COPY %t0
|
|
PseudoBR %bb.3
|
|
|
|
bb.3:
|
|
%stval:vr = PHI %t4, %bb.1, %ldval, %bb.2
|
|
$v0 = COPY %mask
|
|
PseudoVSOXEI64_V_M1_MF8_MASK killed %stval, killed %b, %idxs, $v0, -1, 3
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: if_in_loop
|
|
tracksRegLiveness: true
|
|
body: |
|
|
; CHECK-LABEL: name: if_in_loop
|
|
; CHECK: bb.0:
|
|
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
|
; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: %dst:gpr = COPY $x10
|
|
; CHECK-NEXT: %src:gpr = COPY $x11
|
|
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $x12
|
|
; CHECK-NEXT: %tc:gpr = COPY $x13
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x14
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15
|
|
; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB
|
|
; CHECK-NEXT: %inc:gpr = SRLI %vlenb, 3
|
|
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
|
|
; CHECK-NEXT: PseudoBR %bb.1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1:
|
|
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[COPY3]]
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
|
|
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[ADD]], -1 /* vl=VLMAX */, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1 /* vl=VLMAX */, 6 /* e64 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSLTU_VX_M1_]], -1 /* vl=VLMAX */, 0 /* e8 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3
|
|
; CHECK-NEXT: PseudoBR %bb.2
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2:
|
|
; CHECK-NEXT: successors: %bb.3(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %src, [[COPY3]]
|
|
; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 undef $noreg, [[ADD1]], -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
|
|
; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 undef $noreg, [[PseudoVLE8_V_MF8_]], 4, -1 /* vl=VLMAX */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %dst, [[COPY3]]
|
|
; CHECK-NEXT: PseudoVSE8_V_MF8 [[PseudoVADD_VI_MF8_]], [[ADD2]], -1 /* vl=VLMAX */, 3 /* e8 */, implicit $vl, implicit $vtype
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.3:
|
|
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = ADD [[COPY3]], %inc
|
|
; CHECK-NEXT: BLTU [[COPY3]], %tc, %bb.1
|
|
; CHECK-NEXT: PseudoBR %bb.4
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.4:
|
|
; CHECK-NEXT: PseudoRET
|
|
bb.0:
|
|
successors: %bb.1(0x80000000)
|
|
liveins: $x10, $x11, $x12, $x13, $x14, $x15
|
|
|
|
%dst:gpr = COPY $x10
|
|
%src:gpr = COPY $x11
|
|
%48:gpr = COPY $x12
|
|
%tc:gpr = COPY $x13
|
|
%11:gpr = COPY $x14
|
|
%12:gpr = COPY $x15
|
|
%vlenb:gpr = PseudoReadVLENB
|
|
%inc:gpr = SRLI killed %vlenb, 3
|
|
%10:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 0
|
|
%59:gpr = COPY $x0
|
|
PseudoBR %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.2(0x40000000), %bb.3(0x40000000)
|
|
|
|
%26:gpr = PHI %59, %bb.0, %28, %bb.3
|
|
%61:gpr = ADD %12, %26
|
|
%27:vr = PseudoVADD_VX_M1 undef $noreg, %10, killed %61, -1, 6, 0
|
|
%62:vr = PseudoVMSLTU_VX_M1 %27, %11, -1, 6
|
|
%63:gpr = PseudoVCPOP_M_B64 %62, -1, 0
|
|
%64:gpr = COPY $x0
|
|
BEQ killed %63, %64, %bb.3
|
|
PseudoBR %bb.2
|
|
|
|
bb.2:
|
|
successors: %bb.3(0x80000000)
|
|
|
|
%66:gpr = ADD %src, %26
|
|
%67:vrnov0 = PseudoVLE8_V_MF8 undef $noreg, killed %66, -1, 3, 0
|
|
%76:vrnov0 = PseudoVADD_VI_MF8 undef $noreg, %67, 4, -1, 3, 0
|
|
%77:gpr = ADD %dst, %26
|
|
PseudoVSE8_V_MF8 killed %76, killed %77, -1, 3
|
|
|
|
bb.3:
|
|
successors: %bb.1(0x7c000000), %bb.4(0x04000000)
|
|
|
|
%28:gpr = ADD %26, %inc
|
|
BLTU %28, %tc, %bb.1
|
|
PseudoBR %bb.4
|
|
|
|
bb.4:
|
|
PseudoRET
|
|
|
|
...
|
|
---
|
|
name: pre_undemanded_vl
|
|
body: |
|
|
; CHECK-LABEL: name: pre_undemanded_vl
|
|
; CHECK: bb.0:
|
|
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
|
|
; CHECK-NEXT: PseudoBR %bb.1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1:
|
|
; CHECK-NEXT: successors: %bb.1(0x80000000)
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S undef $noreg, 6 /* e64 */, implicit $vtype
|
|
; CHECK-NEXT: PseudoBR %bb.1
|
|
bb.0:
|
|
PseudoBR %bb.1
|
|
bb.1:
|
|
%x:gpr = PseudoVMV_X_S undef $noreg, 6
|
|
PseudoBR %bb.1
|
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...
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---
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name: clobberred_forwarded_avl
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: clobberred_forwarded_avl
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $x10, $v8m2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %avl:gprnox0 = COPY $x10
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY %avl
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; CHECK-NEXT: dead %outvl:gprnox0 = PseudoVSETVLI %avl, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $v8m2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead %avl:gprnox0 = ADDI %avl, 1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: liveins: $v8m2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, renamable $v8m2, renamable $v8m2, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, renamable $v8m2, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoRET implicit $v8m2
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bb.0:
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liveins: $x10, $v8m2
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%avl:gprnox0 = COPY $x10
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%outvl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype
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bb.1:
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liveins: $v8m2
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%avl:gprnox0 = ADDI %avl:gprnox0, 1
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bb.2:
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liveins: $v8m2
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renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, renamable $v8m2, renamable $v8m2, -1, 5, 0
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renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, killed renamable $v8m2, %outvl:gprnox0, 5, 0
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PseudoRET implicit $v8m2
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...
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---
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name: clobberred_forwarded_phi_avl
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: clobberred_forwarded_phi_avl
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x10, $x11, $v8m2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %v:vrm2 = COPY $v8m2
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; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 1
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; CHECK-NEXT: %x:gpr = COPY $x10
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; CHECK-NEXT: %y:gpr = COPY $x11
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; CHECK-NEXT: BEQ %x, %y, %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY [[ADDI]]
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; CHECK-NEXT: dead %outvl:gprnox0 = PseudoVSETVLI [[ADDI]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: dead [[ADDI:%[0-9]+]]:gprnox0 = ADDI [[ADDI]], 1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, %v, $noreg /* vl */, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoRET implicit $v8m2
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bb.0:
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liveins: $x10, $x11, $v8m2
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%v:vrm2 = COPY $v8m2
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%a:gpr = ADDI $x0, 1
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%x:gpr = COPY $x10
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%y:gpr = COPY $x11
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BEQ %x, %y, %bb.2
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bb.1:
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%b:gpr = ADDI $x0, 2
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bb.2:
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%avl:gprnox0 = PHI %a, %bb.0, %b, %bb.1
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%outvl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype
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bb.3:
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%avl:gprnox0 = ADDI %avl:gprnox0, 1
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bb.4:
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renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1, 5, 0
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renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, killed %v, %outvl:gprnox0, 5, 0
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PseudoRET implicit $v8m2
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...
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---
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name: avl_is_last_instr
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: avl_is_last_instr
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $x10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %avl:gprnox0 = COPY $x10
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY %avl
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: dead %avl:gprnox0 = ADDI %avl, -1
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: $v8 = PseudoVMV_S_X undef renamable $v8, $x0, 1 /* vl */, 3 /* e8 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: $v8 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, $noreg /* vl */, 3 /* e8 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
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bb.0:
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liveins: $x10
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%avl:gprnox0 = COPY $x10
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bb.1:
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%vl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 192, implicit-def dead $vl, implicit-def dead $vtype
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%avl:gprnox0 = ADDI %avl:gprnox0, -1
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$v8 = PseudoVMV_S_X undef renamable $v8, $x0, 1, 3
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$v8 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %vl:gprnox0, 3, 3
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