derek.holloway
7502bf64a4
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259 lines
8.4 KiB
LLVM
259 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32V
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64V
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define <vscale x 8 x i64> @vsplat_nxv8i64_1() {
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; CHECK-LABEL: vsplat_nxv8i64_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v8, -1
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; CHECK-NEXT: ret
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ret <vscale x 8 x i64> splat (i64 -1)
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}
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define <vscale x 8 x i64> @vsplat_nxv8i64_2() {
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; CHECK-LABEL: vsplat_nxv8i64_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v8, 4
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; CHECK-NEXT: ret
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ret <vscale x 8 x i64> splat (i64 4)
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}
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define <vscale x 8 x i64> @vsplat_nxv8i64_3() {
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; CHECK-LABEL: vsplat_nxv8i64_3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 255
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; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a0
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; CHECK-NEXT: ret
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ret <vscale x 8 x i64> splat (i64 255)
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}
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define <vscale x 8 x i64> @vsplat_nxv8i64_4() {
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; RV32V-LABEL: vsplat_nxv8i64_4:
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; RV32V: # %bb.0:
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; RV32V-NEXT: addi sp, sp, -16
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; RV32V-NEXT: .cfi_def_cfa_offset 16
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; RV32V-NEXT: lui a0, 1028096
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; RV32V-NEXT: addi a0, a0, -1281
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; RV32V-NEXT: sw a0, 8(sp)
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; RV32V-NEXT: sw zero, 12(sp)
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; RV32V-NEXT: addi a0, sp, 8
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; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV32V-NEXT: vlse64.v v8, (a0), zero
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; RV32V-NEXT: addi sp, sp, 16
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; RV32V-NEXT: .cfi_def_cfa_offset 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_nxv8i64_4:
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; RV64V: # %bb.0:
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; RV64V-NEXT: li a0, 251
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; RV64V-NEXT: slli a0, a0, 24
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; RV64V-NEXT: addi a0, a0, -1281
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; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV64V-NEXT: vmv.v.x v8, a0
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; RV64V-NEXT: ret
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ret <vscale x 8 x i64> splat (i64 4211079935)
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}
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define <vscale x 8 x i64> @vsplat_nxv8i64_5(i64 %a) {
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; RV32V-LABEL: vsplat_nxv8i64_5:
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; RV32V: # %bb.0:
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; RV32V-NEXT: addi sp, sp, -16
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; RV32V-NEXT: .cfi_def_cfa_offset 16
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; RV32V-NEXT: sw a0, 8(sp)
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; RV32V-NEXT: sw a1, 12(sp)
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; RV32V-NEXT: addi a0, sp, 8
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; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV32V-NEXT: vlse64.v v8, (a0), zero
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; RV32V-NEXT: addi sp, sp, 16
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; RV32V-NEXT: .cfi_def_cfa_offset 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_nxv8i64_5:
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; RV64V: # %bb.0:
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; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV64V-NEXT: vmv.v.x v8, a0
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; RV64V-NEXT: ret
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%head = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
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%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x i64> %splat
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}
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define <vscale x 8 x i64> @vadd_vx_nxv8i64_6(<vscale x 8 x i64> %v) {
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; CHECK-LABEL: vadd_vx_nxv8i64_6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; CHECK-NEXT: vadd.vi v8, v8, 2
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; CHECK-NEXT: ret
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%vret = add <vscale x 8 x i64> %v, splat (i64 2)
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ret <vscale x 8 x i64> %vret
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}
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define <vscale x 8 x i64> @vadd_vx_nxv8i64_7(<vscale x 8 x i64> %v) {
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; CHECK-LABEL: vadd_vx_nxv8i64_7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; CHECK-NEXT: vadd.vi v8, v8, -1
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; CHECK-NEXT: ret
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%vret = add <vscale x 8 x i64> %v, splat (i64 -1)
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ret <vscale x 8 x i64> %vret
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}
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define <vscale x 8 x i64> @vadd_vx_nxv8i64_8(<vscale x 8 x i64> %v) {
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; CHECK-LABEL: vadd_vx_nxv8i64_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 255
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; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; CHECK-NEXT: vadd.vx v8, v8, a0
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; CHECK-NEXT: ret
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%vret = add <vscale x 8 x i64> %v, splat (i64 255)
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ret <vscale x 8 x i64> %vret
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}
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define <vscale x 8 x i64> @vadd_vx_nxv8i64_9(<vscale x 8 x i64> %v) {
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; CHECK-LABEL: vadd_vx_nxv8i64_9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 503808
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; CHECK-NEXT: addi a0, a0, -1281
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; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; CHECK-NEXT: vadd.vx v8, v8, a0
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; CHECK-NEXT: ret
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%vret = add <vscale x 8 x i64> %v, splat (i64 2063596287)
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ret <vscale x 8 x i64> %vret
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}
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define <vscale x 8 x i64> @vadd_vx_nxv8i64_10(<vscale x 8 x i64> %v) {
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; RV32V-LABEL: vadd_vx_nxv8i64_10:
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; RV32V: # %bb.0:
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; RV32V-NEXT: addi sp, sp, -16
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; RV32V-NEXT: .cfi_def_cfa_offset 16
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; RV32V-NEXT: lui a0, 1028096
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; RV32V-NEXT: addi a0, a0, -1281
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; RV32V-NEXT: sw a0, 8(sp)
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; RV32V-NEXT: sw zero, 12(sp)
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; RV32V-NEXT: addi a0, sp, 8
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; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV32V-NEXT: vlse64.v v16, (a0), zero
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; RV32V-NEXT: vadd.vv v8, v8, v16
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; RV32V-NEXT: addi sp, sp, 16
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; RV32V-NEXT: .cfi_def_cfa_offset 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vadd_vx_nxv8i64_10:
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; RV64V: # %bb.0:
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; RV64V-NEXT: li a0, 251
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; RV64V-NEXT: slli a0, a0, 24
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; RV64V-NEXT: addi a0, a0, -1281
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; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV64V-NEXT: vadd.vx v8, v8, a0
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; RV64V-NEXT: ret
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%vret = add <vscale x 8 x i64> %v, splat (i64 4211079935)
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ret <vscale x 8 x i64> %vret
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}
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define <vscale x 8 x i64> @vadd_vx_nxv8i64_11(<vscale x 8 x i64> %v) {
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; RV32V-LABEL: vadd_vx_nxv8i64_11:
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; RV32V: # %bb.0:
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; RV32V-NEXT: addi sp, sp, -16
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; RV32V-NEXT: .cfi_def_cfa_offset 16
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; RV32V-NEXT: li a0, 1
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; RV32V-NEXT: lui a1, 1028096
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; RV32V-NEXT: addi a1, a1, -1281
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; RV32V-NEXT: sw a1, 8(sp)
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; RV32V-NEXT: sw a0, 12(sp)
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; RV32V-NEXT: addi a0, sp, 8
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; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV32V-NEXT: vlse64.v v16, (a0), zero
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; RV32V-NEXT: vadd.vv v8, v8, v16
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; RV32V-NEXT: addi sp, sp, 16
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; RV32V-NEXT: .cfi_def_cfa_offset 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vadd_vx_nxv8i64_11:
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; RV64V: # %bb.0:
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; RV64V-NEXT: li a0, 507
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; RV64V-NEXT: slli a0, a0, 24
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; RV64V-NEXT: addi a0, a0, -1281
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; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV64V-NEXT: vadd.vx v8, v8, a0
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; RV64V-NEXT: ret
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%vret = add <vscale x 8 x i64> %v, splat (i64 8506047231)
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ret <vscale x 8 x i64> %vret
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}
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define <vscale x 8 x i64> @vadd_vx_nxv8i64_12(<vscale x 8 x i64> %v, i64 %a) {
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; RV32V-LABEL: vadd_vx_nxv8i64_12:
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; RV32V: # %bb.0:
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; RV32V-NEXT: addi sp, sp, -16
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; RV32V-NEXT: .cfi_def_cfa_offset 16
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; RV32V-NEXT: sw a0, 8(sp)
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; RV32V-NEXT: sw a1, 12(sp)
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; RV32V-NEXT: addi a0, sp, 8
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; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV32V-NEXT: vlse64.v v16, (a0), zero
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; RV32V-NEXT: vadd.vv v8, v8, v16
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; RV32V-NEXT: addi sp, sp, 16
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; RV32V-NEXT: .cfi_def_cfa_offset 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vadd_vx_nxv8i64_12:
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; RV64V: # %bb.0:
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; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV64V-NEXT: vadd.vx v8, v8, a0
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; RV64V-NEXT: ret
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%head = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
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%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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%vret = add <vscale x 8 x i64> %v, %splat
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ret <vscale x 8 x i64> %vret
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}
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define <vscale x 8 x i64> @vsplat_nxv8i64_13(i32 %a) {
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; RV32V-LABEL: vsplat_nxv8i64_13:
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; RV32V: # %bb.0:
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; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV32V-NEXT: vmv.v.x v8, a0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_nxv8i64_13:
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; RV64V: # %bb.0:
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; RV64V-NEXT: sext.w a0, a0
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; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV64V-NEXT: vmv.v.x v8, a0
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; RV64V-NEXT: ret
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%b = sext i32 %a to i64
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%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
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%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x i64> %splat
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}
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define <vscale x 8 x i64> @vsplat_nxv8i64_14(i32 %a) {
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; RV32V-LABEL: vsplat_nxv8i64_14:
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; RV32V: # %bb.0:
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; RV32V-NEXT: addi sp, sp, -16
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; RV32V-NEXT: .cfi_def_cfa_offset 16
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; RV32V-NEXT: sw a0, 8(sp)
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; RV32V-NEXT: sw zero, 12(sp)
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; RV32V-NEXT: addi a0, sp, 8
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; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV32V-NEXT: vlse64.v v8, (a0), zero
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; RV32V-NEXT: addi sp, sp, 16
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; RV32V-NEXT: .cfi_def_cfa_offset 0
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; RV32V-NEXT: ret
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;
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; RV64V-LABEL: vsplat_nxv8i64_14:
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; RV64V: # %bb.0:
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; RV64V-NEXT: slli a0, a0, 32
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; RV64V-NEXT: srli a0, a0, 32
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; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma
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; RV64V-NEXT: vmv.v.x v8, a0
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; RV64V-NEXT: ret
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%b = zext i32 %a to i64
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%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
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%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
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ret <vscale x 8 x i64> %splat
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}
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