derek.holloway
7502bf64a4
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56 lines
2.5 KiB
LLVM
56 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK
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define <vscale x 2 x i1> @vsub_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsub_vv_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i1> @llvm.vp.sub.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %b, <vscale x 2 x i1> %m, i32 %evl)
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ret <vscale x 2 x i1> %v
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}
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define <vscale x 4 x i1> @vsub_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsub_vv_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i1> @llvm.vp.sub.nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %b, <vscale x 4 x i1> %m, i32 %evl)
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ret <vscale x 4 x i1> %v
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}
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define <vscale x 8 x i1> @vsub_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsub_vv_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i1> @llvm.vp.sub.nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %b, <vscale x 8 x i1> %m, i32 %evl)
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ret <vscale x 8 x i1> %v
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}
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define <vscale x 16 x i1> @vsub_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsub_vv_nxv16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i1> @llvm.vp.sub.nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %b, <vscale x 16 x i1> %m, i32 %evl)
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ret <vscale x 16 x i1> %v
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}
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define <vscale x 32 x i1> @vsub_vv_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vsub_vv_nxv32i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vmxor.mm v0, v0, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x i1> @llvm.vp.sub.nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %b, <vscale x 32 x i1> %m, i32 %evl)
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ret <vscale x 32 x i1> %v
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}
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