derek.holloway
7502bf64a4
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247 lines
11 KiB
LLVM
247 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 2 x i7> @vtrunc_nxv2i7_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i7_nxv2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i7> @llvm.vp.trunc.nxv2i7.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)
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ret <vscale x 2 x i7> %v
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}
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define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i15(<vscale x 2 x i15> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i8_nxv2i15:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i15(<vscale x 2 x i15> %a, <vscale x 2 x i1> %m, i32 %vl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i8_nxv2i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i16_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i8_nxv2i16_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i8_nxv2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i32_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i8_nxv2i32_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i8_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 2 x i8> @vtrunc_nxv2i8_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i8_nxv2i64_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v10, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i8> @llvm.vp.trunc.nxv2i8.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
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ret <vscale x 2 x i8> %v
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}
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define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i16_nxv2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)
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ret <vscale x 2 x i16> %v
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}
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define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i32_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i16_nxv2i32_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v8, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
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ret <vscale x 2 x i16> %v
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}
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define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i16_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v10, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)
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ret <vscale x 2 x i16> %v
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}
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define <vscale x 2 x i16> @vtrunc_nxv2i16_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i16_nxv2i64_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v10, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
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ret <vscale x 2 x i16> %v
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}
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define <vscale x 15 x i16> @vtrunc_nxv15i16_nxv15i64(<vscale x 15 x i64> %a, <vscale x 15 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv15i16_nxv15i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vnsrl.wi v24, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v24, 0
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vnsrl.wi v12, v16, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v12, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 15 x i16> @llvm.vp.trunc.nxv15i16.nxv15i64(<vscale x 15 x i64> %a, <vscale x 15 x i1> %m, i32 %vl)
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ret <vscale x 15 x i16> %v
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}
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define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i32_nxv2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i32> @llvm.vp.trunc.nxv2i32.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %m, i32 %vl)
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ret <vscale x 2 x i32> %v
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}
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define <vscale x 2 x i32> @vtrunc_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i64> %a, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv2i32_nxv2i64_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v8, 0
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i32> @llvm.vp.trunc.nxv2i32.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)
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ret <vscale x 2 x i32> %v
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}
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define <vscale x 32 x i7> @vtrunc_nxv32i7_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv32i7_nxv32i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vnsrl.wi v24, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v24, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vnsrl.wi v12, v16, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v12, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x i7> @llvm.vp.trunc.nxv32i7.nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 %vl)
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ret <vscale x 32 x i7> %v
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}
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define <vscale x 32 x i8> @vtrunc_nxv32i8_nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv32i8_nxv32i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vnsrl.wi v24, v8, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v24, 0
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vnsrl.wi v12, v16, 0
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v10, v12, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x i8> @llvm.vp.trunc.nxv32i8.nxv32i32(<vscale x 32 x i32> %a, <vscale x 32 x i1> %m, i32 %vl)
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ret <vscale x 32 x i8> %v
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}
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define <vscale x 32 x i32> @vtrunc_nxv32i64_nxv32i32(<vscale x 32 x i64> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {
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; CHECK-LABEL: vtrunc_nxv32i64_nxv32i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: sub sp, sp, a1
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
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; CHECK-NEXT: addi a1, sp, 16
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; CHECK-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
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; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv8r.v v0, v8
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: vl8re64.v v16, (a0)
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: add a0, a0, a1
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; CHECK-NEXT: vl8re64.v v8, (a0)
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; CHECK-NEXT: vnsrl.wi v24, v0, 0
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; CHECK-NEXT: vnsrl.wi v0, v16, 0
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; CHECK-NEXT: vnsrl.wi v4, v8, 0
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
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; CHECK-NEXT: vnsrl.wi v28, v8, 0
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; CHECK-NEXT: vmv8r.v v8, v24
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: .cfi_def_cfa sp, 16
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: .cfi_def_cfa_offset 0
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; CHECK-NEXT: ret
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%v = call <vscale x 32 x i32> @llvm.vp.trunc.nxv32i32.nxv32i64(<vscale x 32 x i64> %a, <vscale x 32 x i1> %m, i32 %vl)
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ret <vscale x 32 x i32> %v
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}
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