derek.holloway
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38 lines
2.5 KiB
LLVM
38 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x i32> @vwmacc_vv_nxv1i32_unmasked_tu(<vscale x 1 x i16> %a,
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; CHECK-LABEL: vwmacc_vv_nxv1i32_unmasked_tu:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
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; CHECK-NEXT: vwmaccsu.vv v10, v8, v9
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
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<vscale x 1 x i16> %b, <vscale x 1 x i32> %c, i32 zeroext %evl) {
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%aext = call <vscale x 1 x i32> @llvm.vp.sext.nxv1i32.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
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%bext = call <vscale x 1 x i32> @llvm.vp.zext.nxv1i32.nxv1i16(<vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
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%abmul = call <vscale x 1 x i32> @llvm.vp.mul.nxv1i32(<vscale x 1 x i32> %aext, <vscale x 1 x i32> %bext, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
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%cadd = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %abmul, <vscale x 1 x i32> %c, <vscale x 1 x i1>splat (i1 -1), i32 %evl)
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%ret = call <vscale x 1 x i32> @llvm.vp.merge.nxv1i32(<vscale x 1 x i1> splat (i1 -1), <vscale x 1 x i32> %cadd, <vscale x 1 x i32> %c, i32 %evl)
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ret <vscale x 1 x i32> %ret
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}
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define <vscale x 1 x i32> @vwmacc_vv_nxv1i32_commute_unmasked_tu(<vscale x 1 x i16> %a,
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; CHECK-LABEL: vwmacc_vv_nxv1i32_commute_unmasked_tu:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
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; CHECK-NEXT: vwmaccsu.vv v10, v9, v8
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
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<vscale x 1 x i16> %b, <vscale x 1 x i32> %c, i32 zeroext %evl) {
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%aext = call <vscale x 1 x i32> @llvm.vp.zext.nxv1i32.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
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%bext = call <vscale x 1 x i32> @llvm.vp.sext.nxv1i32.nxv1i16(<vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
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%abmul = call <vscale x 1 x i32> @llvm.vp.mul.nxv1i32(<vscale x 1 x i32> %aext, <vscale x 1 x i32> %bext, <vscale x 1 x i1> splat (i1 -1), i32 %evl)
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%cadd = call <vscale x 1 x i32> @llvm.vp.add.nxv1i32(<vscale x 1 x i32> %abmul, <vscale x 1 x i32> %c, <vscale x 1 x i1>splat (i1 -1), i32 %evl)
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%ret = call <vscale x 1 x i32> @llvm.vp.merge.nxv1i32(<vscale x 1 x i1> splat (i1 -1), <vscale x 1 x i32> %cadd, <vscale x 1 x i32> %c, i32 %evl)
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ret <vscale x 1 x i32> %ret
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}
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