TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+m,+v  -o - %s \
# RUN:   -start-before=prologepilog | FileCheck %s
#
# These tests check that we are assigning the right stack slot to GPRs and to
# vector registers (VRs). If this test changes, make sure there is no overlap
# between slots for GPRs and VRs.
--- |
  define void @foo() #0 {
  ; CHECK-LABEL: foo:
  ; CHECK:       # %bb.0: # %entry
  ; CHECK-NEXT:    addi sp, sp, -32
  ; CHECK-NEXT:    sw s9, 28(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    csrr a1, vlenb
  ; CHECK-NEXT:    slli a1, a1, 1
  ; CHECK-NEXT:    sub sp, sp, a1
  ; CHECK-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    addi a0, sp, 16
  ; CHECK-NEXT:    vs2r.v v30, (a0) # vscale x 16-byte Folded Spill
  ; CHECK-NEXT:    csrr a0, vlenb
  ; CHECK-NEXT:    slli a0, a0, 1
  ; CHECK-NEXT:    add sp, sp, a0
  ; CHECK-NEXT:    lw s9, 28(sp) # 4-byte Folded Reload
  ; CHECK-NEXT:    addi sp, sp, 32
  ; CHECK-NEXT:    ret
  entry:
    ret void
  }

  define void @rvv_clobbers_callee_save() #0 {
  ; CHECK-LABEL: rvv_clobbers_callee_save:
  ; CHECK:       # %bb.0: # %entry
  ; CHECK-NEXT:    addi sp, sp, -80
  ; CHECK-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    sw s9, 68(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    addi s0, sp, 80
  ; CHECK-NEXT:    csrr a1, vlenb
  ; CHECK-NEXT:    slli a1, a1, 1
  ; CHECK-NEXT:    sub sp, sp, a1
  ; CHECK-NEXT:    andi sp, sp, -32
  ; CHECK-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    addi a0, sp, 64
  ; CHECK-NEXT:    vs2r.v v30, (a0) # vscale x 16-byte Folded Spill
  ; CHECK-NEXT:    addi sp, s0, -80
  ; CHECK-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
  ; CHECK-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
  ; CHECK-NEXT:    lw s9, 68(sp) # 4-byte Folded Reload
  ; CHECK-NEXT:    addi sp, sp, 80
  ; CHECK-NEXT:    ret
  entry:
    ret void
  }

  attributes #0 = { nounwind }
...
---
name:            foo
alignment:       2
frameInfo:
  maxAlignment:    8
stack:
  - { id: 0, type: spill-slot, size: 4, alignment: 4 }
  - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10, $v30m2

    $x25 = COPY $x10
    SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)
    VS2R_V renamable $v30m2, %stack.1 :: (store (<vscale x 2 x s64>) into %stack.1, align 8)
    PseudoRET

...
---
name:            rvv_clobbers_callee_save
alignment:       2
frameInfo:
  maxAlignment:    8
stack:
  - { id: 0, type: spill-slot, size: 4, alignment: 32 }
  - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10, $v30m2

    $x25 = COPY $x10
    SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)
    VS2R_V renamable $v30m2, %stack.1 :: (store (<vscale x 2 x s64>) into %stack.1, align 8)
    PseudoRET

...