derek.holloway
7502bf64a4
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64 lines
2.6 KiB
LLVM
64 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+prefer-w-inst \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 1 x i8> @vrol_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
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; CHECK-LABEL: vrol_vx_nxv1i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addiw a0, a0, 1
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; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vrol.vx v8, v8, a0
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; CHECK-NEXT: ret
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%s = add i8 %b, 1
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%b.head = insertelement <vscale x 1 x i8> poison, i8 %s, i32 0
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%b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
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%x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)
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ret <vscale x 1 x i8> %x
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}
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define <vscale x 1 x i8> @vror_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
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; CHECK-LABEL: vror_vx_nxv1i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addiw a0, a0, 1
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; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vror.vx v8, v8, a0
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; CHECK-NEXT: ret
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%s = add i8 %b, 1
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%b.head = insertelement <vscale x 1 x i8> poison, i8 %s, i32 0
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%b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
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%x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)
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ret <vscale x 1 x i8> %x
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}
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define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b) {
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; CHECK-LABEL: vwsll_vx_i8_nxv2i64_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv1r.v v10, v8
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; CHECK-NEXT: addiw a0, a0, 1
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; CHECK-NEXT: vwsll.vx v8, v10, a0
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; CHECK-NEXT: ret
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%s = add i8 %b, 1
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%head = insertelement <vscale x 2 x i8> poison, i8 %s, i32 0
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%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 1 x i8> @vandn_vx_nxv1i8(i8 %x, <vscale x 1 x i8> %y) {
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; CHECK-LABEL: vandn_vx_nxv1i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addiw a0, a0, 1
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; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vandn.vx v8, v8, a0
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; CHECK-NEXT: ret
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%s = add i8 %x, 1
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%a = xor i8 %s, -1
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%head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 0
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%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
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%b = and <vscale x 1 x i8> %splat, %y
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ret <vscale x 1 x i8> %b
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}
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