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TheRock/compiler/amd-llvm/llvm/test/CodeGen/RISCV/rvv/zvfofp8min-alt-interlave.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+experimental-zvfofp8min \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+experimental-zvfofp8min \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
; a -> need alt
; n -> don't need alt
; d -> don't care alt
define <vscale x 1 x bfloat> @test_a_n_interleave(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: test_a_n_interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8alt, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.alt.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %0,
iXLen 7, iXLen %1)
%b = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8(
<vscale x 1 x bfloat> poison,
<vscale x 1 x i8> %a,
iXLen %1)
ret <vscale x 1 x bfloat> %b
}
define <vscale x 1 x i8> @test_a_n_a_interleave(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: test_a_n_a_interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8alt, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e8alt, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.alt.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %0,
iXLen 7, iXLen %1)
%b = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8(
<vscale x 1 x bfloat> poison,
<vscale x 1 x i8> %a,
iXLen %1)
%c = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.alt.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %b,
iXLen 7, iXLen %1)
ret <vscale x 1 x i8> %c
}
define <vscale x 1 x i8> @test_a_n_d_interleave(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: test_a_n_d_interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8alt, mf8, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.alt.nxv1bf16.nxv1i8(
<vscale x 1 x bfloat> poison,
<vscale x 1 x i8> %0,
iXLen %1)
%b = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %a,
iXLen 7, iXLen %1)
%c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8(
<vscale x 1 x i8> poison,
<vscale x 1 x i8> %b,
<vscale x 1 x i8> %b,
iXLen %1)
ret <vscale x 1 x i8> %c
}
define <vscale x 1 x i8> @test_a_n_a_d_interleave(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: test_a_n_a_d_interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8alt, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8alt, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
; CHECK-NEXT: vadd.vv v8, v9, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.alt.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %0,
iXLen 7, iXLen %1)
%b = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8(
<vscale x 1 x bfloat> poison,
<vscale x 1 x i8> %a,
iXLen %1)
%c = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.alt.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %b,
iXLen 7, iXLen %1)
%d = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8(
<vscale x 1 x i8> poison,
<vscale x 1 x i8> %c,
<vscale x 1 x i8> %c,
iXLen %1)
ret <vscale x 1 x i8> %d
}
define <vscale x 1 x bfloat> @test_n_a_interleave(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: test_n_a_interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8alt, mf8, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %0,
iXLen 7, iXLen %1)
%b = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.alt.nxv1bf16.nxv1i8(
<vscale x 1 x bfloat> poison,
<vscale x 1 x i8> %a,
iXLen %1)
ret <vscale x 1 x bfloat> %b
}
define <vscale x 1 x i8> @test_n_a_n_interleave(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: test_n_a_n_interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8alt, mf8, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %0,
iXLen 7, iXLen %1)
%b = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.alt.nxv1bf16.nxv1i8(
<vscale x 1 x bfloat> poison,
<vscale x 1 x i8> %a,
iXLen %1)
%c = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %b,
iXLen 7, iXLen %1)
ret <vscale x 1 x i8> %c
}
define <vscale x 1 x i8> @test_n_a_d_interleave(<vscale x 1 x i8> %0, iXLen %1) nounwind {
; CHECK-LABEL: test_n_a_d_interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8alt, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.nxv1bf16.nxv1i8(
<vscale x 1 x bfloat> poison,
<vscale x 1 x i8> %0,
iXLen %1)
%b = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.alt.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %a,
iXLen 7, iXLen %1)
%c = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8(
<vscale x 1 x i8> poison,
<vscale x 1 x i8> %b,
<vscale x 1 x i8> %b,
iXLen %1)
ret <vscale x 1 x i8> %c
}
define <vscale x 1 x i8> @test_n_a_n_d_interleave(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {
; CHECK-LABEL: test_n_a_n_d_interleave:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e8alt, mf8, ta, ma
; CHECK-NEXT: vfwcvtbf16.f.f.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vfncvtbf16.f.f.w v9, v8
; CHECK-NEXT: vadd.vv v8, v9, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %0,
iXLen 7, iXLen %1)
%b = call <vscale x 1 x bfloat> @llvm.riscv.vfwcvt.f.f.v.alt.nxv1bf16.nxv1i8(
<vscale x 1 x bfloat> poison,
<vscale x 1 x i8> %a,
iXLen %1)
%c = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.w.nxv1i8.nxv1bf16(
<vscale x 1 x i8> poison,
<vscale x 1 x bfloat> %b,
iXLen 7, iXLen %1)
%d = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8(
<vscale x 1 x i8> poison,
<vscale x 1 x i8> %c,
<vscale x 1 x i8> %c,
iXLen %1)
ret <vscale x 1 x i8> %d
}
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