derek.holloway
7502bf64a4
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704 lines
26 KiB
LLVM
704 lines
26 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s --check-prefixes=RV32I-ZBB
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; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=RV64I-ZBB
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; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb,+short-forward-branch-ialu | \
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; RUN: FileCheck %s --check-prefixes=RV32I-SFB-ZBB
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; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+short-forward-branch-ialu | \
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; RUN: FileCheck %s --check-prefixes=RV64I-SFB-ZBB
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; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb,+short-forward-branch-iminmax | \
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; RUN: FileCheck %s --check-prefixes=RV32I-SFBIMinMax-ZBB
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; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb,+short-forward-branch-iminmax | \
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; RUN: FileCheck %s --check-prefixes=RV64I-SFBIMinMax-ZBB
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define i32 @select_example_smax(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
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; RV32I-ZBB-LABEL: select_example_smax:
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; RV32I-ZBB: # %bb.0: # %entry
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; RV32I-ZBB-NEXT: beqz a2, .LBB0_2
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; RV32I-ZBB-NEXT: # %bb.1:
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; RV32I-ZBB-NEXT: max a1, a0, a3
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; RV32I-ZBB-NEXT: .LBB0_2: # %entry
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; RV32I-ZBB-NEXT: mv a0, a1
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; RV32I-ZBB-NEXT: ret
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;
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; RV64I-ZBB-LABEL: select_example_smax:
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; RV64I-ZBB: # %bb.0: # %entry
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; RV64I-ZBB-NEXT: beqz a2, .LBB0_2
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; RV64I-ZBB-NEXT: # %bb.1:
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; RV64I-ZBB-NEXT: sext.w a3, a3
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; RV64I-ZBB-NEXT: sext.w a0, a0
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; RV64I-ZBB-NEXT: max a1, a0, a3
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; RV64I-ZBB-NEXT: .LBB0_2: # %entry
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; RV64I-ZBB-NEXT: mv a0, a1
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; RV64I-ZBB-NEXT: ret
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;
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; RV32I-SFB-ZBB-LABEL: select_example_smax:
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; RV32I-SFB-ZBB: # %bb.0: # %entry
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; RV32I-SFB-ZBB-NEXT: max a0, a0, a3
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; RV32I-SFB-ZBB-NEXT: bnez a2, .LBB0_2
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; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry
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; RV32I-SFB-ZBB-NEXT: mv a0, a1
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; RV32I-SFB-ZBB-NEXT: .LBB0_2: # %entry
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; RV32I-SFB-ZBB-NEXT: ret
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;
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; RV64I-SFB-ZBB-LABEL: select_example_smax:
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; RV64I-SFB-ZBB: # %bb.0: # %entry
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; RV64I-SFB-ZBB-NEXT: sext.w a3, a3
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; RV64I-SFB-ZBB-NEXT: sext.w a0, a0
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; RV64I-SFB-ZBB-NEXT: max a0, a0, a3
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; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB0_2
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; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry
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; RV64I-SFB-ZBB-NEXT: mv a0, a1
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; RV64I-SFB-ZBB-NEXT: .LBB0_2: # %entry
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; RV64I-SFB-ZBB-NEXT: ret
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;
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; RV32I-SFBIMinMax-ZBB-LABEL: select_example_smax:
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; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB0_2
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; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: max a1, a0, a3
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; RV32I-SFBIMinMax-ZBB-NEXT: .LBB0_2: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a1
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; RV32I-SFBIMinMax-ZBB-NEXT: ret
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;
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; RV64I-SFBIMinMax-ZBB-LABEL: select_example_smax:
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; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a3, a3
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; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a0, a0
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; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB0_2
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; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: max a1, a0, a3
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; RV64I-SFBIMinMax-ZBB-NEXT: .LBB0_2: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1
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; RV64I-SFBIMinMax-ZBB-NEXT: ret
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entry:
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%res = call i32 @llvm.smax.i32(i32 %a, i32 %y)
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%sel = select i1 %x, i32 %res, i32 %b
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ret i32 %sel
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}
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define i32 @select_example_smin(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
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; RV32I-ZBB-LABEL: select_example_smin:
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; RV32I-ZBB: # %bb.0: # %entry
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; RV32I-ZBB-NEXT: beqz a2, .LBB1_2
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; RV32I-ZBB-NEXT: # %bb.1:
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; RV32I-ZBB-NEXT: min a1, a0, a3
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; RV32I-ZBB-NEXT: .LBB1_2: # %entry
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; RV32I-ZBB-NEXT: mv a0, a1
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; RV32I-ZBB-NEXT: ret
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;
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; RV64I-ZBB-LABEL: select_example_smin:
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; RV64I-ZBB: # %bb.0: # %entry
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; RV64I-ZBB-NEXT: beqz a2, .LBB1_2
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; RV64I-ZBB-NEXT: # %bb.1:
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; RV64I-ZBB-NEXT: sext.w a3, a3
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; RV64I-ZBB-NEXT: sext.w a0, a0
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; RV64I-ZBB-NEXT: min a1, a0, a3
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; RV64I-ZBB-NEXT: .LBB1_2: # %entry
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; RV64I-ZBB-NEXT: mv a0, a1
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; RV64I-ZBB-NEXT: ret
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;
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; RV32I-SFB-ZBB-LABEL: select_example_smin:
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; RV32I-SFB-ZBB: # %bb.0: # %entry
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; RV32I-SFB-ZBB-NEXT: min a0, a0, a3
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; RV32I-SFB-ZBB-NEXT: bnez a2, .LBB1_2
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; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry
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; RV32I-SFB-ZBB-NEXT: mv a0, a1
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; RV32I-SFB-ZBB-NEXT: .LBB1_2: # %entry
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; RV32I-SFB-ZBB-NEXT: ret
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;
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; RV64I-SFB-ZBB-LABEL: select_example_smin:
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; RV64I-SFB-ZBB: # %bb.0: # %entry
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; RV64I-SFB-ZBB-NEXT: sext.w a3, a3
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; RV64I-SFB-ZBB-NEXT: sext.w a0, a0
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; RV64I-SFB-ZBB-NEXT: min a0, a0, a3
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; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB1_2
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; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry
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; RV64I-SFB-ZBB-NEXT: mv a0, a1
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; RV64I-SFB-ZBB-NEXT: .LBB1_2: # %entry
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; RV64I-SFB-ZBB-NEXT: ret
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;
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; RV32I-SFBIMinMax-ZBB-LABEL: select_example_smin:
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; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB1_2
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; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: min a1, a0, a3
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; RV32I-SFBIMinMax-ZBB-NEXT: .LBB1_2: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a1
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; RV32I-SFBIMinMax-ZBB-NEXT: ret
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;
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; RV64I-SFBIMinMax-ZBB-LABEL: select_example_smin:
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; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a3, a3
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; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a0, a0
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; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB1_2
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; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: min a1, a0, a3
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; RV64I-SFBIMinMax-ZBB-NEXT: .LBB1_2: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1
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; RV64I-SFBIMinMax-ZBB-NEXT: ret
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entry:
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%res = call i32 @llvm.smin.i32(i32 %a, i32 %y)
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%sel = select i1 %x, i32 %res, i32 %b
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ret i32 %sel
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}
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define i32 @select_example_umax(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
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; RV32I-ZBB-LABEL: select_example_umax:
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; RV32I-ZBB: # %bb.0: # %entry
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; RV32I-ZBB-NEXT: beqz a2, .LBB2_2
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; RV32I-ZBB-NEXT: # %bb.1:
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; RV32I-ZBB-NEXT: maxu a1, a0, a3
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; RV32I-ZBB-NEXT: .LBB2_2: # %entry
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; RV32I-ZBB-NEXT: mv a0, a1
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; RV32I-ZBB-NEXT: ret
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;
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; RV64I-ZBB-LABEL: select_example_umax:
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; RV64I-ZBB: # %bb.0: # %entry
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; RV64I-ZBB-NEXT: beqz a2, .LBB2_2
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; RV64I-ZBB-NEXT: # %bb.1:
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; RV64I-ZBB-NEXT: sext.w a3, a3
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; RV64I-ZBB-NEXT: sext.w a0, a0
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; RV64I-ZBB-NEXT: maxu a1, a0, a3
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; RV64I-ZBB-NEXT: .LBB2_2: # %entry
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; RV64I-ZBB-NEXT: mv a0, a1
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; RV64I-ZBB-NEXT: ret
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;
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; RV32I-SFB-ZBB-LABEL: select_example_umax:
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; RV32I-SFB-ZBB: # %bb.0: # %entry
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; RV32I-SFB-ZBB-NEXT: maxu a0, a0, a3
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; RV32I-SFB-ZBB-NEXT: bnez a2, .LBB2_2
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; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry
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; RV32I-SFB-ZBB-NEXT: mv a0, a1
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; RV32I-SFB-ZBB-NEXT: .LBB2_2: # %entry
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; RV32I-SFB-ZBB-NEXT: ret
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;
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; RV64I-SFB-ZBB-LABEL: select_example_umax:
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; RV64I-SFB-ZBB: # %bb.0: # %entry
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; RV64I-SFB-ZBB-NEXT: sext.w a3, a3
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; RV64I-SFB-ZBB-NEXT: sext.w a0, a0
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; RV64I-SFB-ZBB-NEXT: maxu a0, a0, a3
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; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB2_2
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; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry
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; RV64I-SFB-ZBB-NEXT: mv a0, a1
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; RV64I-SFB-ZBB-NEXT: .LBB2_2: # %entry
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; RV64I-SFB-ZBB-NEXT: ret
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;
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; RV32I-SFBIMinMax-ZBB-LABEL: select_example_umax:
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; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB2_2
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; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: maxu a1, a0, a3
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; RV32I-SFBIMinMax-ZBB-NEXT: .LBB2_2: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a1
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; RV32I-SFBIMinMax-ZBB-NEXT: ret
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;
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; RV64I-SFBIMinMax-ZBB-LABEL: select_example_umax:
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; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a3, a3
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; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a0, a0
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; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB2_2
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; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: maxu a1, a0, a3
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; RV64I-SFBIMinMax-ZBB-NEXT: .LBB2_2: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1
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; RV64I-SFBIMinMax-ZBB-NEXT: ret
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entry:
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%res = call i32 @llvm.umax.i32(i32 %a, i32 %y)
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%sel = select i1 %x, i32 %res, i32 %b
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ret i32 %sel
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}
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define i32 @select_example_umin(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
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; RV32I-ZBB-LABEL: select_example_umin:
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; RV32I-ZBB: # %bb.0: # %entry
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; RV32I-ZBB-NEXT: beqz a2, .LBB3_2
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; RV32I-ZBB-NEXT: # %bb.1:
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; RV32I-ZBB-NEXT: minu a1, a0, a3
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; RV32I-ZBB-NEXT: .LBB3_2: # %entry
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; RV32I-ZBB-NEXT: mv a0, a1
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; RV32I-ZBB-NEXT: ret
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;
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; RV64I-ZBB-LABEL: select_example_umin:
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; RV64I-ZBB: # %bb.0: # %entry
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; RV64I-ZBB-NEXT: beqz a2, .LBB3_2
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; RV64I-ZBB-NEXT: # %bb.1:
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; RV64I-ZBB-NEXT: sext.w a3, a3
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; RV64I-ZBB-NEXT: sext.w a0, a0
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; RV64I-ZBB-NEXT: minu a1, a0, a3
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; RV64I-ZBB-NEXT: .LBB3_2: # %entry
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; RV64I-ZBB-NEXT: mv a0, a1
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; RV64I-ZBB-NEXT: ret
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;
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; RV32I-SFB-ZBB-LABEL: select_example_umin:
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; RV32I-SFB-ZBB: # %bb.0: # %entry
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; RV32I-SFB-ZBB-NEXT: minu a0, a0, a3
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; RV32I-SFB-ZBB-NEXT: bnez a2, .LBB3_2
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; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry
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; RV32I-SFB-ZBB-NEXT: mv a0, a1
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; RV32I-SFB-ZBB-NEXT: .LBB3_2: # %entry
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; RV32I-SFB-ZBB-NEXT: ret
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;
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; RV64I-SFB-ZBB-LABEL: select_example_umin:
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; RV64I-SFB-ZBB: # %bb.0: # %entry
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; RV64I-SFB-ZBB-NEXT: sext.w a3, a3
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; RV64I-SFB-ZBB-NEXT: sext.w a0, a0
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; RV64I-SFB-ZBB-NEXT: minu a0, a0, a3
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; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB3_2
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; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry
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; RV64I-SFB-ZBB-NEXT: mv a0, a1
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; RV64I-SFB-ZBB-NEXT: .LBB3_2: # %entry
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; RV64I-SFB-ZBB-NEXT: ret
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;
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; RV32I-SFBIMinMax-ZBB-LABEL: select_example_umin:
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; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB3_2
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; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: minu a1, a0, a3
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; RV32I-SFBIMinMax-ZBB-NEXT: .LBB3_2: # %entry
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; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a1
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; RV32I-SFBIMinMax-ZBB-NEXT: ret
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;
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; RV64I-SFBIMinMax-ZBB-LABEL: select_example_umin:
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; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a3, a3
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; RV64I-SFBIMinMax-ZBB-NEXT: sext.w a0, a0
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; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB3_2
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; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: minu a1, a0, a3
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; RV64I-SFBIMinMax-ZBB-NEXT: .LBB3_2: # %entry
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; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1
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; RV64I-SFBIMinMax-ZBB-NEXT: ret
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entry:
|
|
%res = call i32 @llvm.umin.i32(i32 %a, i32 %y)
|
|
%sel = select i1 %x, i32 %res, i32 %b
|
|
ret i32 %sel
|
|
}
|
|
|
|
define i64 @select_example_smax_1(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {
|
|
; RV32I-ZBB-LABEL: select_example_smax_1:
|
|
; RV32I-ZBB: # %bb.0: # %entry
|
|
; RV32I-ZBB-NEXT: beq a1, a6, .LBB4_2
|
|
; RV32I-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-ZBB-NEXT: slt a7, a6, a1
|
|
; RV32I-ZBB-NEXT: beqz a7, .LBB4_3
|
|
; RV32I-ZBB-NEXT: j .LBB4_4
|
|
; RV32I-ZBB-NEXT: .LBB4_2:
|
|
; RV32I-ZBB-NEXT: sltu a7, a5, a0
|
|
; RV32I-ZBB-NEXT: bnez a7, .LBB4_4
|
|
; RV32I-ZBB-NEXT: .LBB4_3: # %entry
|
|
; RV32I-ZBB-NEXT: mv a1, a6
|
|
; RV32I-ZBB-NEXT: mv a0, a5
|
|
; RV32I-ZBB-NEXT: .LBB4_4: # %entry
|
|
; RV32I-ZBB-NEXT: beqz a4, .LBB4_6
|
|
; RV32I-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-ZBB-NEXT: ret
|
|
; RV32I-ZBB-NEXT: .LBB4_6: # %entry
|
|
; RV32I-ZBB-NEXT: mv a0, a2
|
|
; RV32I-ZBB-NEXT: mv a1, a3
|
|
; RV32I-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-ZBB-LABEL: select_example_smax_1:
|
|
; RV64I-ZBB: # %bb.0: # %entry
|
|
; RV64I-ZBB-NEXT: beqz a2, .LBB4_2
|
|
; RV64I-ZBB-NEXT: # %bb.1:
|
|
; RV64I-ZBB-NEXT: max a1, a0, a3
|
|
; RV64I-ZBB-NEXT: .LBB4_2: # %entry
|
|
; RV64I-ZBB-NEXT: mv a0, a1
|
|
; RV64I-ZBB-NEXT: ret
|
|
;
|
|
; RV32I-SFB-ZBB-LABEL: select_example_smax_1:
|
|
; RV32I-SFB-ZBB: # %bb.0: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: sltu a7, a5, a0
|
|
; RV32I-SFB-ZBB-NEXT: slt t0, a6, a1
|
|
; RV32I-SFB-ZBB-NEXT: bne a1, a6, .LBB4_2
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv t0, a7
|
|
; RV32I-SFB-ZBB-NEXT: .LBB4_2: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB4_4
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.3: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a1, a6
|
|
; RV32I-SFB-ZBB-NEXT: .LBB4_4: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB4_6
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a0, a5
|
|
; RV32I-SFB-ZBB-NEXT: .LBB4_6: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB4_8
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.7: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a0, a2
|
|
; RV32I-SFB-ZBB-NEXT: .LBB4_8: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB4_10
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.9: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a1, a3
|
|
; RV32I-SFB-ZBB-NEXT: .LBB4_10: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-SFB-ZBB-LABEL: select_example_smax_1:
|
|
; RV64I-SFB-ZBB: # %bb.0: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: max a0, a0, a3
|
|
; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB4_2
|
|
; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: mv a0, a1
|
|
; RV64I-SFB-ZBB-NEXT: .LBB4_2: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: ret
|
|
;
|
|
; RV32I-SFBIMinMax-ZBB-LABEL: select_example_smax_1:
|
|
; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: sltu a7, a5, a0
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: slt t0, a6, a1
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bne a1, a6, .LBB4_2
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv t0, a7
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_2: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB4_4
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.3: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_4: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB4_6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a5
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_6: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB4_8
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.7: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a2
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_8: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB4_10
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.9: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a3
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB4_10: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-SFBIMinMax-ZBB-LABEL: select_example_smax_1:
|
|
; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB4_2
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: max a1, a0, a3
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: .LBB4_2: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: ret
|
|
entry:
|
|
%res = call i64 @llvm.smax.i64(i64 %a, i64 %y)
|
|
%sel = select i1 %x, i64 %res, i64 %b
|
|
ret i64 %sel
|
|
}
|
|
|
|
define i64 @select_example_smin_1(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {
|
|
; RV32I-ZBB-LABEL: select_example_smin_1:
|
|
; RV32I-ZBB: # %bb.0: # %entry
|
|
; RV32I-ZBB-NEXT: beq a1, a6, .LBB5_2
|
|
; RV32I-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-ZBB-NEXT: slt a7, a1, a6
|
|
; RV32I-ZBB-NEXT: beqz a7, .LBB5_3
|
|
; RV32I-ZBB-NEXT: j .LBB5_4
|
|
; RV32I-ZBB-NEXT: .LBB5_2:
|
|
; RV32I-ZBB-NEXT: sltu a7, a0, a5
|
|
; RV32I-ZBB-NEXT: bnez a7, .LBB5_4
|
|
; RV32I-ZBB-NEXT: .LBB5_3: # %entry
|
|
; RV32I-ZBB-NEXT: mv a1, a6
|
|
; RV32I-ZBB-NEXT: mv a0, a5
|
|
; RV32I-ZBB-NEXT: .LBB5_4: # %entry
|
|
; RV32I-ZBB-NEXT: beqz a4, .LBB5_6
|
|
; RV32I-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-ZBB-NEXT: ret
|
|
; RV32I-ZBB-NEXT: .LBB5_6: # %entry
|
|
; RV32I-ZBB-NEXT: mv a0, a2
|
|
; RV32I-ZBB-NEXT: mv a1, a3
|
|
; RV32I-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-ZBB-LABEL: select_example_smin_1:
|
|
; RV64I-ZBB: # %bb.0: # %entry
|
|
; RV64I-ZBB-NEXT: beqz a2, .LBB5_2
|
|
; RV64I-ZBB-NEXT: # %bb.1:
|
|
; RV64I-ZBB-NEXT: min a1, a0, a3
|
|
; RV64I-ZBB-NEXT: .LBB5_2: # %entry
|
|
; RV64I-ZBB-NEXT: mv a0, a1
|
|
; RV64I-ZBB-NEXT: ret
|
|
;
|
|
; RV32I-SFB-ZBB-LABEL: select_example_smin_1:
|
|
; RV32I-SFB-ZBB: # %bb.0: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: sltu a7, a0, a5
|
|
; RV32I-SFB-ZBB-NEXT: slt t0, a1, a6
|
|
; RV32I-SFB-ZBB-NEXT: bne a1, a6, .LBB5_2
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv t0, a7
|
|
; RV32I-SFB-ZBB-NEXT: .LBB5_2: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB5_4
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.3: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a1, a6
|
|
; RV32I-SFB-ZBB-NEXT: .LBB5_4: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB5_6
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a0, a5
|
|
; RV32I-SFB-ZBB-NEXT: .LBB5_6: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB5_8
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.7: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a0, a2
|
|
; RV32I-SFB-ZBB-NEXT: .LBB5_8: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB5_10
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.9: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a1, a3
|
|
; RV32I-SFB-ZBB-NEXT: .LBB5_10: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-SFB-ZBB-LABEL: select_example_smin_1:
|
|
; RV64I-SFB-ZBB: # %bb.0: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: min a0, a0, a3
|
|
; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB5_2
|
|
; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: mv a0, a1
|
|
; RV64I-SFB-ZBB-NEXT: .LBB5_2: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: ret
|
|
;
|
|
; RV32I-SFBIMinMax-ZBB-LABEL: select_example_smin_1:
|
|
; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: sltu a7, a0, a5
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: slt t0, a1, a6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bne a1, a6, .LBB5_2
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv t0, a7
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_2: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB5_4
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.3: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_4: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB5_6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a5
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_6: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB5_8
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.7: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a2
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_8: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB5_10
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.9: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a3
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB5_10: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-SFBIMinMax-ZBB-LABEL: select_example_smin_1:
|
|
; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB5_2
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: min a1, a0, a3
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: .LBB5_2: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: ret
|
|
entry:
|
|
%res = call i64 @llvm.smin.i64(i64 %a, i64 %y)
|
|
%sel = select i1 %x, i64 %res, i64 %b
|
|
ret i64 %sel
|
|
}
|
|
|
|
define i64 @select_example_umax_1(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {
|
|
; RV32I-ZBB-LABEL: select_example_umax_1:
|
|
; RV32I-ZBB: # %bb.0: # %entry
|
|
; RV32I-ZBB-NEXT: beq a1, a6, .LBB6_2
|
|
; RV32I-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-ZBB-NEXT: sltu a7, a6, a1
|
|
; RV32I-ZBB-NEXT: beqz a7, .LBB6_3
|
|
; RV32I-ZBB-NEXT: j .LBB6_4
|
|
; RV32I-ZBB-NEXT: .LBB6_2:
|
|
; RV32I-ZBB-NEXT: sltu a7, a5, a0
|
|
; RV32I-ZBB-NEXT: bnez a7, .LBB6_4
|
|
; RV32I-ZBB-NEXT: .LBB6_3: # %entry
|
|
; RV32I-ZBB-NEXT: mv a1, a6
|
|
; RV32I-ZBB-NEXT: mv a0, a5
|
|
; RV32I-ZBB-NEXT: .LBB6_4: # %entry
|
|
; RV32I-ZBB-NEXT: beqz a4, .LBB6_6
|
|
; RV32I-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-ZBB-NEXT: ret
|
|
; RV32I-ZBB-NEXT: .LBB6_6: # %entry
|
|
; RV32I-ZBB-NEXT: mv a0, a2
|
|
; RV32I-ZBB-NEXT: mv a1, a3
|
|
; RV32I-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-ZBB-LABEL: select_example_umax_1:
|
|
; RV64I-ZBB: # %bb.0: # %entry
|
|
; RV64I-ZBB-NEXT: beqz a2, .LBB6_2
|
|
; RV64I-ZBB-NEXT: # %bb.1:
|
|
; RV64I-ZBB-NEXT: maxu a1, a0, a3
|
|
; RV64I-ZBB-NEXT: .LBB6_2: # %entry
|
|
; RV64I-ZBB-NEXT: mv a0, a1
|
|
; RV64I-ZBB-NEXT: ret
|
|
;
|
|
; RV32I-SFB-ZBB-LABEL: select_example_umax_1:
|
|
; RV32I-SFB-ZBB: # %bb.0: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: sltu a7, a5, a0
|
|
; RV32I-SFB-ZBB-NEXT: sltu t0, a6, a1
|
|
; RV32I-SFB-ZBB-NEXT: bne a1, a6, .LBB6_2
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv t0, a7
|
|
; RV32I-SFB-ZBB-NEXT: .LBB6_2: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB6_4
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.3: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a1, a6
|
|
; RV32I-SFB-ZBB-NEXT: .LBB6_4: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB6_6
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a0, a5
|
|
; RV32I-SFB-ZBB-NEXT: .LBB6_6: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB6_8
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.7: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a0, a2
|
|
; RV32I-SFB-ZBB-NEXT: .LBB6_8: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB6_10
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.9: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a1, a3
|
|
; RV32I-SFB-ZBB-NEXT: .LBB6_10: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-SFB-ZBB-LABEL: select_example_umax_1:
|
|
; RV64I-SFB-ZBB: # %bb.0: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: maxu a0, a0, a3
|
|
; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB6_2
|
|
; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: mv a0, a1
|
|
; RV64I-SFB-ZBB-NEXT: .LBB6_2: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: ret
|
|
;
|
|
; RV32I-SFBIMinMax-ZBB-LABEL: select_example_umax_1:
|
|
; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: sltu a7, a5, a0
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: sltu t0, a6, a1
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bne a1, a6, .LBB6_2
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv t0, a7
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_2: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB6_4
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.3: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_4: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB6_6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a5
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_6: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB6_8
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.7: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a2
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_8: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB6_10
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.9: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a3
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB6_10: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-SFBIMinMax-ZBB-LABEL: select_example_umax_1:
|
|
; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB6_2
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: maxu a1, a0, a3
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: .LBB6_2: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: ret
|
|
entry:
|
|
%res = call i64 @llvm.umax.i64(i64 %a, i64 %y)
|
|
%sel = select i1 %x, i64 %res, i64 %b
|
|
ret i64 %sel
|
|
}
|
|
|
|
define i64 @select_example_umin_1(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {
|
|
; RV32I-ZBB-LABEL: select_example_umin_1:
|
|
; RV32I-ZBB: # %bb.0: # %entry
|
|
; RV32I-ZBB-NEXT: beq a1, a6, .LBB7_2
|
|
; RV32I-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-ZBB-NEXT: sltu a7, a1, a6
|
|
; RV32I-ZBB-NEXT: beqz a7, .LBB7_3
|
|
; RV32I-ZBB-NEXT: j .LBB7_4
|
|
; RV32I-ZBB-NEXT: .LBB7_2:
|
|
; RV32I-ZBB-NEXT: sltu a7, a0, a5
|
|
; RV32I-ZBB-NEXT: bnez a7, .LBB7_4
|
|
; RV32I-ZBB-NEXT: .LBB7_3: # %entry
|
|
; RV32I-ZBB-NEXT: mv a1, a6
|
|
; RV32I-ZBB-NEXT: mv a0, a5
|
|
; RV32I-ZBB-NEXT: .LBB7_4: # %entry
|
|
; RV32I-ZBB-NEXT: beqz a4, .LBB7_6
|
|
; RV32I-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-ZBB-NEXT: ret
|
|
; RV32I-ZBB-NEXT: .LBB7_6: # %entry
|
|
; RV32I-ZBB-NEXT: mv a0, a2
|
|
; RV32I-ZBB-NEXT: mv a1, a3
|
|
; RV32I-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-ZBB-LABEL: select_example_umin_1:
|
|
; RV64I-ZBB: # %bb.0: # %entry
|
|
; RV64I-ZBB-NEXT: beqz a2, .LBB7_2
|
|
; RV64I-ZBB-NEXT: # %bb.1:
|
|
; RV64I-ZBB-NEXT: minu a1, a0, a3
|
|
; RV64I-ZBB-NEXT: .LBB7_2: # %entry
|
|
; RV64I-ZBB-NEXT: mv a0, a1
|
|
; RV64I-ZBB-NEXT: ret
|
|
;
|
|
; RV32I-SFB-ZBB-LABEL: select_example_umin_1:
|
|
; RV32I-SFB-ZBB: # %bb.0: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: sltu a7, a0, a5
|
|
; RV32I-SFB-ZBB-NEXT: sltu t0, a1, a6
|
|
; RV32I-SFB-ZBB-NEXT: bne a1, a6, .LBB7_2
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv t0, a7
|
|
; RV32I-SFB-ZBB-NEXT: .LBB7_2: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB7_4
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.3: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a1, a6
|
|
; RV32I-SFB-ZBB-NEXT: .LBB7_4: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez t0, .LBB7_6
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a0, a5
|
|
; RV32I-SFB-ZBB-NEXT: .LBB7_6: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB7_8
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.7: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a0, a2
|
|
; RV32I-SFB-ZBB-NEXT: .LBB7_8: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: bnez a4, .LBB7_10
|
|
; RV32I-SFB-ZBB-NEXT: # %bb.9: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: mv a1, a3
|
|
; RV32I-SFB-ZBB-NEXT: .LBB7_10: # %entry
|
|
; RV32I-SFB-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-SFB-ZBB-LABEL: select_example_umin_1:
|
|
; RV64I-SFB-ZBB: # %bb.0: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: minu a0, a0, a3
|
|
; RV64I-SFB-ZBB-NEXT: bnez a2, .LBB7_2
|
|
; RV64I-SFB-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: mv a0, a1
|
|
; RV64I-SFB-ZBB-NEXT: .LBB7_2: # %entry
|
|
; RV64I-SFB-ZBB-NEXT: ret
|
|
;
|
|
; RV32I-SFBIMinMax-ZBB-LABEL: select_example_umin_1:
|
|
; RV32I-SFBIMinMax-ZBB: # %bb.0: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: sltu a7, a0, a5
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: sltu t0, a1, a6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bne a1, a6, .LBB7_2
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv t0, a7
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_2: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB7_4
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.3: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_4: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez t0, .LBB7_6
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.5: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a5
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_6: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB7_8
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.7: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a0, a2
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_8: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: bnez a4, .LBB7_10
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: # %bb.9: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: mv a1, a3
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: .LBB7_10: # %entry
|
|
; RV32I-SFBIMinMax-ZBB-NEXT: ret
|
|
;
|
|
; RV64I-SFBIMinMax-ZBB-LABEL: select_example_umin_1:
|
|
; RV64I-SFBIMinMax-ZBB: # %bb.0: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: beqz a2, .LBB7_2
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: # %bb.1: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: minu a1, a0, a3
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: .LBB7_2: # %entry
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: mv a0, a1
|
|
; RV64I-SFBIMinMax-ZBB-NEXT: ret
|
|
entry:
|
|
%res = call i64 @llvm.umin.i64(i64 %a, i64 %y)
|
|
%sel = select i1 %x, i64 %res, i64 %b
|
|
ret i64 %sel
|
|
}
|