derek.holloway
7502bf64a4
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419 lines
10 KiB
LLVM
419 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,NOZBS32
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; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,NOZBS64
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; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zbs -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV32,ZBS,ZBS32
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; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zbs -verify-machineinstrs < %s \
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; RUN: | FileCheck %s --check-prefixes=CHECK,RV64,ZBS,ZBS64
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define i32 @and0xabcdefff(i32 %x) {
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; CHECK-LABEL: and0xabcdefff:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a1, 344865
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; CHECK-NEXT: andn a0, a0, a1
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; CHECK-NEXT: ret
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%and = and i32 %x, -1412567041
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ret i32 %and
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}
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define i32 @orlow13(i32 %x) {
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; CHECK-LABEL: orlow13:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a1, 1048574
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; CHECK-NEXT: orn a0, a0, a1
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; CHECK-NEXT: ret
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%or = or i32 %x, 8191
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ret i32 %or
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}
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define i64 @orlow24(i64 %x) {
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; RV32-LABEL: orlow24:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a2, 1044480
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; RV32-NEXT: orn a0, a0, a2
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; RV32-NEXT: ret
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;
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; RV64-LABEL: orlow24:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 1044480
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; RV64-NEXT: orn a0, a0, a1
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; RV64-NEXT: ret
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%or = or i64 %x, 16777215
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ret i64 %or
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}
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define i32 @xorlow16(i32 %x) {
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; CHECK-LABEL: xorlow16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a1, 1048560
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; CHECK-NEXT: xnor a0, a0, a1
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; CHECK-NEXT: ret
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%xor = xor i32 %x, 65535
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ret i32 %xor
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}
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define i32 @xorlow31(i32 %x) {
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; CHECK-LABEL: xorlow31:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a1, 524288
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; CHECK-NEXT: xnor a0, a0, a1
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; CHECK-NEXT: ret
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%xor = xor i32 %x, 2147483647
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ret i32 %xor
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}
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define i32 @oraddlow16(i32 %x) {
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; RV32-LABEL: oraddlow16:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a1, 16
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; RV32-NEXT: addi a1, a1, -1
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; RV32-NEXT: or a0, a0, a1
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: oraddlow16:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 16
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; RV64-NEXT: addi a1, a1, -1
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; RV64-NEXT: or a0, a0, a1
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; RV64-NEXT: addw a0, a0, a1
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; RV64-NEXT: ret
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%or = or i32 %x, 65535
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%add = add nsw i32 %or, 65535
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ret i32 %add
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}
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define i32 @addorlow16(i32 %x) {
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; RV32-LABEL: addorlow16:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a1, 16
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; RV32-NEXT: addi a1, a1, -1
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: or a0, a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: addorlow16:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 16
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; RV64-NEXT: addi a1, a1, -1
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; RV64-NEXT: addw a0, a0, a1
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; RV64-NEXT: or a0, a0, a1
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; RV64-NEXT: ret
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%add = add nsw i32 %x, 65535
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%or = or i32 %add, 65535
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ret i32 %or
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}
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define i32 @andxorlow16(i32 %x) {
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; CHECK-LABEL: andxorlow16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a1, 16
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; CHECK-NEXT: addi a1, a1, -1
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; CHECK-NEXT: andn a0, a1, a0
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; CHECK-NEXT: ret
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%and = and i32 %x, 65535
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%xor = xor i32 %and, 65535
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ret i32 %xor
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}
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define void @orarray100(ptr %a) {
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; RV32-LABEL: orarray100:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: li a2, 0
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; RV32-NEXT: lui a3, 1048560
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; RV32-NEXT: .LBB8_1: # %for.body
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; RV32-NEXT: # =>This Inner Loop Header: Depth=1
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; RV32-NEXT: slli a4, a1, 2
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; RV32-NEXT: addi a1, a1, 1
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; RV32-NEXT: add a4, a0, a4
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; RV32-NEXT: lw a5, 0(a4)
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; RV32-NEXT: seqz a6, a1
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; RV32-NEXT: add a2, a2, a6
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; RV32-NEXT: xori a6, a1, 100
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; RV32-NEXT: orn a5, a5, a3
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; RV32-NEXT: or a6, a6, a2
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; RV32-NEXT: sw a5, 0(a4)
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; RV32-NEXT: bnez a6, .LBB8_1
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; RV32-NEXT: # %bb.2: # %for.cond.cleanup
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; RV32-NEXT: ret
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;
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; RV64-LABEL: orarray100:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addi a1, a0, 400
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; RV64-NEXT: lui a2, 1048560
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; RV64-NEXT: .LBB8_1: # %for.body
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; RV64-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64-NEXT: lw a3, 0(a0)
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; RV64-NEXT: orn a3, a3, a2
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; RV64-NEXT: sw a3, 0(a0)
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; RV64-NEXT: addi a0, a0, 4
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; RV64-NEXT: bne a0, a1, .LBB8_1
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; RV64-NEXT: # %bb.2: # %for.cond.cleanup
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; RV64-NEXT: ret
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entry:
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br label %for.body
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for.cond.cleanup:
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ret void
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds nuw i32, ptr %a, i64 %indvars.iv
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%1 = load i32, ptr %arrayidx, align 4
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%or = or i32 %1, 65535
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store i32 %or, ptr %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, 100
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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define void @orarray3(ptr %a) {
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; CHECK-LABEL: orarray3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a1, 0(a0)
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; CHECK-NEXT: lw a2, 4(a0)
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; CHECK-NEXT: lw a3, 8(a0)
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; CHECK-NEXT: lui a4, 1048560
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; CHECK-NEXT: orn a1, a1, a4
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; CHECK-NEXT: orn a2, a2, a4
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; CHECK-NEXT: orn a3, a3, a4
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: sw a2, 4(a0)
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; CHECK-NEXT: sw a3, 8(a0)
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; CHECK-NEXT: ret
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%1 = load i32, ptr %a, align 4
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%or = or i32 %1, 65535
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store i32 %or, ptr %a, align 4
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%arrayidx.1 = getelementptr inbounds nuw i8, ptr %a, i64 4
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%2 = load i32, ptr %arrayidx.1, align 4
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%or.1 = or i32 %2, 65535
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store i32 %or.1, ptr %arrayidx.1, align 4
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%arrayidx.2 = getelementptr inbounds nuw i8, ptr %a, i64 8
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%3 = load i32, ptr %arrayidx.2, align 4
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%or.2 = or i32 %3, 65535
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store i32 %or.2, ptr %arrayidx.2, align 4
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ret void
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}
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define i32 @andlow16(i32 %x) {
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; CHECK-LABEL: andlow16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: zext.h a0, a0
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; CHECK-NEXT: ret
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%and = and i32 %x, 65535
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ret i32 %and
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}
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define i32 @andlow24(i32 %x) {
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; RV32-LABEL: andlow24:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a0, a0, 8
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; RV32-NEXT: srli a0, a0, 8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: andlow24:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a0, a0, 40
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; RV64-NEXT: srli a0, a0, 40
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; RV64-NEXT: ret
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%and = and i32 %x, 16777215
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ret i32 %and
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}
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define i32 @compl(i32 %x) {
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; CHECK-LABEL: compl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: not a0, a0
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; CHECK-NEXT: ret
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%not = xor i32 %x, -1
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ret i32 %not
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}
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define i32 @orlow12(i32 %x) {
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; NOZBS32-LABEL: orlow12:
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; NOZBS32: # %bb.0:
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; NOZBS32-NEXT: lui a1, 1048575
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; NOZBS32-NEXT: orn a0, a0, a1
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; NOZBS32-NEXT: ret
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;
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; NOZBS64-LABEL: orlow12:
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; NOZBS64: # %bb.0:
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; NOZBS64-NEXT: lui a1, 1048575
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; NOZBS64-NEXT: orn a0, a0, a1
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; NOZBS64-NEXT: ret
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;
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; ZBS-LABEL: orlow12:
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; ZBS: # %bb.0:
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; ZBS-NEXT: ori a0, a0, 2047
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; ZBS-NEXT: bseti a0, a0, 11
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; ZBS-NEXT: ret
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%or = or i32 %x, 4095
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ret i32 %or
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}
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define i32 @xorlow12(i32 %x) {
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; NOZBS32-LABEL: xorlow12:
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; NOZBS32: # %bb.0:
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; NOZBS32-NEXT: lui a1, 1048575
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; NOZBS32-NEXT: xnor a0, a0, a1
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; NOZBS32-NEXT: ret
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;
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; NOZBS64-LABEL: xorlow12:
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; NOZBS64: # %bb.0:
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; NOZBS64-NEXT: lui a1, 1048575
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; NOZBS64-NEXT: xnor a0, a0, a1
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; NOZBS64-NEXT: ret
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;
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; ZBS-LABEL: xorlow12:
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; ZBS: # %bb.0:
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; ZBS-NEXT: xori a0, a0, 2047
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; ZBS-NEXT: binvi a0, a0, 11
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; ZBS-NEXT: ret
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%xor = xor i32 %x, 4095
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ret i32 %xor
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}
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define i64 @andimm64(i64 %x) {
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; RV32-LABEL: andimm64:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a1, 4080
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; RV32-NEXT: andn a0, a0, a1
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; RV32-NEXT: li a1, 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: andimm64:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 983295
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; RV64-NEXT: slli a1, a1, 4
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; RV64-NEXT: andn a0, a0, a1
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; RV64-NEXT: ret
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%and = and i64 %x, 4278255615
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ret i64 %and
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}
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define i64 @orimm64srli(i64 %x) {
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; RV32-LABEL: orimm64srli:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a2, 1040384
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; RV32-NEXT: orn a0, a0, a2
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; RV32-NEXT: lui a2, 917504
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; RV32-NEXT: or a1, a1, a2
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; RV32-NEXT: ret
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;
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; RV64-LABEL: orimm64srli:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 983040
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; RV64-NEXT: srli a1, a1, 3
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; RV64-NEXT: orn a0, a0, a1
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; RV64-NEXT: ret
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%or = or i64 %x, -2305843009180139521
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ret i64 %or
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}
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define i64 @andnofff(i64 %x) {
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; RV32-LABEL: andnofff:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a2, 1044480
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; RV32-NEXT: and a1, a1, a2
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; RV32-NEXT: zext.b a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: andnofff:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 1048560
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; RV64-NEXT: srli a1, a1, 8
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; RV64-NEXT: andn a0, a0, a1
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; RV64-NEXT: ret
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%and = and i64 %x, -72057594037927681
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ret i64 %and
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}
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define i64 @ornofff(i64 %x) {
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; NOZBS32-LABEL: ornofff:
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; NOZBS32: # %bb.0:
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; NOZBS32-NEXT: lui a2, 524288
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; NOZBS32-NEXT: or a1, a1, a2
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; NOZBS32-NEXT: ori a0, a0, 2047
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; NOZBS32-NEXT: ret
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;
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; NOZBS64-LABEL: ornofff:
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; NOZBS64: # %bb.0:
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; NOZBS64-NEXT: lui a1, 1048575
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; NOZBS64-NEXT: srli a1, a1, 1
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; NOZBS64-NEXT: orn a0, a0, a1
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; NOZBS64-NEXT: ret
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;
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; ZBS32-LABEL: ornofff:
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; ZBS32: # %bb.0:
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; ZBS32-NEXT: ori a0, a0, 2047
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; ZBS32-NEXT: bseti a1, a1, 31
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; ZBS32-NEXT: ret
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;
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; ZBS64-LABEL: ornofff:
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; ZBS64: # %bb.0:
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; ZBS64-NEXT: ori a0, a0, 2047
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; ZBS64-NEXT: bseti a0, a0, 63
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; ZBS64-NEXT: ret
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%or = or i64 %x, -9223372036854773761
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ret i64 %or
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}
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define i64 @xornofff(i64 %x) {
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; RV32-LABEL: xornofff:
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; RV32: # %bb.0:
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; RV32-NEXT: lui a2, 983040
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; RV32-NEXT: xor a1, a1, a2
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; RV32-NEXT: xori a0, a0, 255
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; RV32-NEXT: ret
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;
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; RV64-LABEL: xornofff:
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; RV64: # %bb.0:
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; RV64-NEXT: lui a1, 1048575
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; RV64-NEXT: srli a1, a1, 4
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; RV64-NEXT: xnor a0, a0, a1
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; RV64-NEXT: ret
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%xor = xor i64 %x, -1152921504606846721
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ret i64 %xor
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}
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define i64 @and_or_or(i64 %x, i64 %y) {
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; RV32-LABEL: and_or_or:
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; RV32: # %bb.0:
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; RV32-NEXT: ori a1, a1, -2
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; RV32-NEXT: ori a0, a0, 1
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; RV32-NEXT: ori a3, a3, 1
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; RV32-NEXT: ori a2, a2, -2
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; RV32-NEXT: and a0, a0, a2
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; RV32-NEXT: and a1, a1, a3
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|
; RV32-NEXT: ret
|
|
;
|
|
; NOZBS64-LABEL: and_or_or:
|
|
; NOZBS64: # %bb.0:
|
|
; NOZBS64-NEXT: li a2, -1
|
|
; NOZBS64-NEXT: slli a2, a2, 33
|
|
; NOZBS64-NEXT: addi a2, a2, 1
|
|
; NOZBS64-NEXT: or a0, a0, a2
|
|
; NOZBS64-NEXT: li a2, 1
|
|
; NOZBS64-NEXT: slli a2, a2, 33
|
|
; NOZBS64-NEXT: addi a2, a2, -2
|
|
; NOZBS64-NEXT: or a1, a1, a2
|
|
; NOZBS64-NEXT: and a0, a0, a1
|
|
; NOZBS64-NEXT: ret
|
|
;
|
|
; ZBS64-LABEL: and_or_or:
|
|
; ZBS64: # %bb.0:
|
|
; ZBS64-NEXT: bseti a2, zero, 33
|
|
; ZBS64-NEXT: addi a2, a2, -2
|
|
; ZBS64-NEXT: orn a0, a0, a2
|
|
; ZBS64-NEXT: or a1, a1, a2
|
|
; ZBS64-NEXT: and a0, a0, a1
|
|
; ZBS64-NEXT: ret
|
|
%a = or i64 %x, -8589934591
|
|
%b = or i64 %y, 8589934590
|
|
%c = and i64 %a, %b
|
|
ret i64 %c
|
|
}
|