derek.holloway
7502bf64a4
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282 lines
11 KiB
LLVM
282 lines
11 KiB
LLVM
; RUN: llc -O0 --verify-machineinstrs -mtriple=spirv64-amd-amdhsa %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-amd-amdhsa %s -o - -filetype=obj | spirv-val %}
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; CHECK: OpName %[[#KERNEL:]] "kernel"
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; CHECK: OpName %[[#FEATURE_PREDICATE_IDS:]] "llvm.amdgcn.feature.predicate.ids"
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; CHECK: OpName %[[#SET_FPENV_I64:]] "spirv.llvm_set_fpenv_i64"
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; CHECK: OpName %[[#ASHR_PK_I8_I32:]] "spirv.llvm_amdgcn_ashr_pk_i8_i32"
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; CHECK: OpName %[[#S_SLEEP_VAR:]] "spirv.llvm_amdgcn_s_sleep_var"
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; CHECK: OpName %[[#S_WAIT_EVENT_EXPORT_READY:]] "spirv.llvm_amdgcn_s_wait_event_export_ready"
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; CHECK: OpName %[[#S_TTRACEDATA_IMM:]] "spirv.llvm_amdgcn_s_ttracedata_imm"
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; CHECK: OpDecorate %[[#IS_GFX950:]] SpecId 8
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; CHECK: OpDecorate %[[#IS_GFX1201:]] SpecId 3
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; CHECK: OpDecorate %[[#HAS_GFX12_INSTS:]] SpecId 7
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; CHECK: OpDecorate %[[#IS_GFX906:]] SpecId 6
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; CHECK: OpDecorate %[[#IS_GFX1010:]] SpecId 4
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; CHECK: OpDecorate %[[#IS_GFX1101:]] SpecId 5
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; CHECK: OpDecorate %[[#IS_GFX1101_1:]] SpecId 5
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; CHECK: OpDecorate %[[#IS_GFX1010_1:]] SpecId 4
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; CHECK: OpDecorate %[[#IS_GFX1201_1:]] SpecId 3
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; CHECK: OpDecorate %[[#HAS_GFX11_INSTS:]] SpecId 0
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; CHECK: OpDecorate %[[#HAS_GFX10_INSTS:]] SpecId 2
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; CHECK: OpDecorate %[[#HAS_GFX1250_INSTS:]] SpecId 1
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; CHECK: OpDecorate %[[#HAS_GFX11_INSTS_1:]] SpecId 0
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; CHECK: %[[#BOOL:]] = OpTypeBool
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; CHECK: %[[#UCHAR:]] = OpTypeInt 8
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; CHECK: %[[#FEATURE_PREDICATE_IDS_MAP_STRLEN:]] = OpConstant %[[#]] 137
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; CHECK: %[[#FEATURE_PREDICATE_IDS_MAP_STRTY:]] = OpTypeArray %[[#UCHAR]] %[[#FEATURE_PREDICATE_IDS_MAP_STRLEN]]
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; CHECK: %[[#FEATURE_PREDICATE_IDS_MAP_STRVAL:]] = OpConstantComposite %[[#FEATURE_PREDICATE_IDS_MAP_STRTY]]
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; CHECK: %[[#FEATURE_PREDICATE_IDS]] = OpVariable %[[#]] CrossWorkgroup %[[#FEATURE_PREDICATE_IDS_MAP_STRVAL]]
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; CHECK: %[[#IS_GFX950]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#IS_GFX1201]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#HAS_GFX12_INSTS]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#IS_GFX906]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#IS_GFX1010]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#IS_GFX1101]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#IS_GFX1101_1]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#IS_GFX1010_1]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#IS_GFX1201_1]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#HAS_GFX11_INSTS]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#HAS_GFX10_INSTS]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#HAS_GFX1250_INSTS]] = OpSpecConstantFalse %[[#BOOL]]
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; CHECK: %[[#HAS_GFX11_INSTS_1]] = OpSpecConstantFalse %[[#BOOL]]
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declare void @llvm.amdgcn.s.monitor.sleep(i16 immarg) addrspace(4)
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declare void @llvm.amdgcn.s.sleep(i32 immarg) addrspace(4)
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declare i1 @llvm.spv.named.boolean.spec.constant(i32, i1, metadata) addrspace(4)
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declare i16 @llvm.amdgcn.ashr.pk.i8.i32(i32, i32, i32) addrspace(4) #3
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declare void @llvm.set.fpenv.i64(i64) addrspace(4) #4
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declare void @llvm.amdgcn.s.sleep.var(i32) addrspace(4) #5
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declare void @llvm.amdgcn.s.wait.event.export.ready() addrspace(4) #5
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declare void @llvm.amdgcn.s.ttracedata.imm(i16 immarg) addrspace(4) #6
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@p = external addrspace(1) global i32
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@g = external addrspace(1) constant i32
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define void @kernel() addrspace(4) {
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; CHECK-DAG: %[[#KERNEL]] = OpFunction %39 None %40 ; -- Begin function kernel
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; CHECK-NEXT: %2 = OpLabel
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; CHECK-NEXT: %112 = OpLoad %44 %85 Aligned 4
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; CHECK-NEXT: OpBranchConditional %[[#IS_GFX950]] %4 %3
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; CHECK-NEXT: %3 = OpLabel
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; CHECK-NEXT: %113 = OpFunctionCall %39 %[[#SET_FPENV_I64]] %57
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; CHECK-NEXT: OpBranch %5
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; CHECK-NEXT: %4 = OpLabel
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; CHECK-NEXT: %114 = OpFunctionCall %43 %[[#ASHR_PK_I8_I32]] %56 %56 %56
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; CHECK-NEXT: OpBranch %5
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; CHECK-NEXT: %5 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#IS_GFX1201]] %7 %6
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; CHECK-NEXT: %6 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#HAS_GFX12_INSTS]] %7 %8
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; CHECK-NEXT: %7 = OpLabel
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; CHECK-NEXT: %115 = OpFunctionCall %39 %[[#S_SLEEP_VAR]] %112
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; CHECK-NEXT: OpBranch %8
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; CHECK-NEXT: %8 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#IS_GFX906]] %10 %9
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; CHECK-NEXT: %9 = OpLabel
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; CHECK-NEXT: %116 = OpFunctionCall %39 %[[#S_WAIT_EVENT_EXPORT_READY]]
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; CHECK-NEXT: OpBranch %14
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; CHECK-NEXT: %10 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#IS_GFX1010]] %12 %11
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; CHECK-NEXT: %11 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#IS_GFX1101]] %12 %13
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; CHECK-NEXT: %12 = OpLabel
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; CHECK-NEXT: %117 = OpFunctionCall %39 %[[#S_TTRACEDATA_IMM]] %55
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; CHECK-NEXT: OpBranch %13
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; CHECK-NEXT: %13 = OpLabel
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; CHECK-NEXT: OpBranch %14
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; CHECK-NEXT: %14 = OpLabel
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; CHECK-NEXT: OpBranch %15
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; CHECK-NEXT: %15 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#IS_GFX1101_1]] %16 %17
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; CHECK-NEXT: %16 = OpLabel
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; CHECK-NEXT: %118 = OpLoad %44 %97 Aligned 4
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; CHECK-NEXT: %119 = OpIAdd %44 %118 %112
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; CHECK-NEXT: OpStore %97 %119 Aligned 4
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; CHECK-NEXT: OpBranch %17
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; CHECK-NEXT: %17 = OpLabel
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; CHECK-NEXT: OpBranch %18
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; CHECK-NEXT: %18 = OpLabel
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; CHECK-NEXT: %120 = OpLoad %44 %97 Aligned 4
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; CHECK-NEXT: %121 = OpISub %44 %120 %112
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; CHECK-NEXT: OpStore %97 %121 Aligned 4
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; CHECK-NEXT: OpBranch %19
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; CHECK-NEXT: %19 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#IS_GFX1010_1]] %20 %21
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; CHECK-NEXT: %20 = OpLabel
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; CHECK-NEXT: OpBranch %21
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; CHECK-NEXT: %21 = OpLabel
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; CHECK-NEXT: %122 = OpPhi %48 %54 %19 %54 %20
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; CHECK-NEXT: OpBranchConditional %122 %18 %22
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; CHECK-NEXT: %22 = OpLabel
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; CHECK-NEXT: OpBranch %23
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; CHECK-NEXT: %23 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#IS_GFX1201_1]] %24 %25
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; CHECK-NEXT: %24 = OpLabel
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; CHECK-NEXT: OpBranch %25
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; CHECK-NEXT: %25 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#HAS_GFX11_INSTS]] %29 %26
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; CHECK-NEXT: %26 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#HAS_GFX10_INSTS]] %27 %28
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; CHECK-NEXT: %27 = OpLabel
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; CHECK-NEXT: %123 = OpFunctionCall %39 %[[#S_TTRACEDATA_IMM]] %55
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; CHECK-NEXT: OpBranch %28
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; CHECK-NEXT: %28 = OpLabel
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; CHECK-NEXT: OpBranch %30
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; CHECK-NEXT: %29 = OpLabel
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; CHECK-NEXT: %124 = OpFunctionCall %39 %[[#S_WAIT_EVENT_EXPORT_READY]]
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; CHECK-NEXT: OpBranch %30
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; CHECK-NEXT: %30 = OpLabel
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; CHECK-NEXT: OpBranch %31
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; CHECK-NEXT: %31 = OpLabel
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; CHECK-NEXT: %125 = OpLoad %44 %97 Aligned 4
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; CHECK-NEXT: %126 = OpISub %44 %125 %112
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; CHECK-NEXT: OpStore %97 %126 Aligned 4
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; CHECK-NEXT: OpBranch %32
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; CHECK-NEXT: %32 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#HAS_GFX1250_INSTS]] %33 %34
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; CHECK-NEXT: %33 = OpLabel
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; CHECK-NEXT: OpBranch %34
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; CHECK-NEXT: %34 = OpLabel
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; CHECK-NEXT: %127 = OpPhi %48 %54 %32 %54 %33
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; CHECK-NEXT: OpBranchConditional %127 %31 %35
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; CHECK-NEXT: %35 = OpLabel
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; CHECK-NEXT: OpBranch %36
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; CHECK-NEXT: %36 = OpLabel
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; CHECK-NEXT: OpBranchConditional %[[#HAS_GFX11_INSTS_1]] %37 %38
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entry:
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%x = load i32, ptr addrspace(1) @g
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%is.gfx950. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !9)
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br i1 %is.gfx950., label %cond.true, label %cond.false
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cond.true:
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%0 = call addrspace(4) i16 @llvm.amdgcn.ashr.pk.i8.i32(i32 8, i32 8, i32 8)
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br label %cond.end
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cond.false:
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call addrspace(4) void @llvm.set.fpenv.i64(i64 -1)
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br label %cond.end
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cond.end:
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%is.gfx1201. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !10)
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br i1 %is.gfx1201., label %if.then, label %lor.lhs.false
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lor.lhs.false:
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%has.gfx12-insts. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !11)
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br i1 %has.gfx12-insts., label %if.then, label %if.end
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if.then:
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call addrspace(4) void @llvm.amdgcn.s.sleep.var(i32 %x)
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br label %if.end
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if.end:
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%is.gfx906. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !12)
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br i1 %is.gfx906., label %if.else, label %if.then2
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if.then2:
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call addrspace(4) void @llvm.amdgcn.s.wait.event.export.ready()
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br label %if.end6
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if.else:
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%is.gfx1010. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !13)
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br i1 %is.gfx1010., label %if.then4, label %lor.lhs.false3
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lor.lhs.false3:
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%is.gfx1101. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !14)
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br i1 %is.gfx1101., label %if.then4, label %if.end5
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if.then4:
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call addrspace(4) void @llvm.amdgcn.s.ttracedata.imm(i16 1)
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br label %if.end5
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if.end5:
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br label %if.end6
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if.end6:
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br label %while.cond
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while.cond:
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%is.gfx1101.7 = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !14)
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br i1 %is.gfx1101.7, label %while.body, label %while.end
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while.body:
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%4 = load i32, ptr addrspace(1) @p
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%add = add i32 %4, %x
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store i32 %add, ptr addrspace(1) @p
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br label %while.end
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while.end:
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br label %do.body
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do.body:
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%7 = load i32, ptr addrspace(1) @p
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%sub = sub i32 %7, %x
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store i32 %sub, ptr addrspace(1) @p
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br label %do.cond
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do.cond:
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%is.gfx1010.8 = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !13)
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br i1 %is.gfx1010.8, label %land.rhs, label %land.end
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land.rhs:
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br label %land.end
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land.end:
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%c = phi i1 [ false, %do.cond ], [ false, %land.rhs ]
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br i1 %c, label %do.body, label %do.end
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do.end:
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br label %for.cond
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for.cond:
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%is.gfx1201.9 = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !10)
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br i1 %is.gfx1201.9, label %for.body, label %for.end
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for.body:
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br label %for.end
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for.inc:
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%9 = load i32, ptr addrspace(1) @p
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%inc = add i32 %9, 1
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store i32 %inc, ptr addrspace(1) @p
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br label %for.cond
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for.end:
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%has.gfx11-insts. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !18)
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br i1 %has.gfx11-insts., label %if.then10, label %if.else11
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if.then10:
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call addrspace(4) void @llvm.amdgcn.s.wait.event.export.ready()
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br label %if.end14
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if.else11:
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%has.gfx10-insts. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !19)
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br i1 %has.gfx10-insts., label %if.then12, label %if.end13
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if.then12:
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call addrspace(4) void @llvm.amdgcn.s.ttracedata.imm(i16 1)
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br label %if.end13
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if.end13:
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br label %if.end14
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if.end14:
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br label %do.body15
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do.body15:
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%12 = load i32, ptr addrspace(1) @p
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%sub16 = sub i32 %12, %x
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store i32 %sub16, ptr addrspace(1) @p
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br label %do.cond17
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do.cond17:
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%has.gfx1250-insts. = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !20)
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br i1 %has.gfx1250-insts., label %land.rhs9, label %land.end10
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land.rhs9:
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br label %land.end10
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land.end10:
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%c1 = phi i1 [ false, %do.cond17 ], [ false, %land.rhs9 ]
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br i1 %c1, label %do.body15, label %do.end18
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do.end18:
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br label %for.cond19
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for.cond19:
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%has.gfx11-insts.20 = call addrspace(4) i1 @llvm.spv.named.boolean.spec.constant(i32 -1, i1 false, metadata !18)
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br i1 %has.gfx11-insts.20, label %for.body21, label %for.end24
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for.body21:
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br label %for.end24
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for.inc22:
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%14 = load i32, ptr addrspace(1) @p
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%inc23 = add i32 %14, 1
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store i32 %inc23, ptr addrspace(1) @p
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br label %for.cond19
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for.end24:
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ret void
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}
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!9 = !{!"is.gfx950"}
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!10 = !{!"is.gfx1201"}
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!11 = !{!"has.gfx12-insts"}
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!12 = !{!"is.gfx906"}
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!13 = !{!"is.gfx1010"}
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!14 = !{!"is.gfx1101"}
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!18 = !{!"has.gfx11-insts"}
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!19 = !{!"has.gfx10-insts"}
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!20 = !{!"has.gfx1250-insts"}
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