derek.holloway
7502bf64a4
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60 lines
2.5 KiB
LLVM
60 lines
2.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv1.5-vulkan-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.5-vulkan-unknown %s -o - -filetype=obj | spirv-val %}
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; Test lowering to spir-v backend for various types and scalar/vector
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; CHECK: Capability Shader
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; CHECK: Capability GroupNonUniformShuffle
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; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0
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; CHECK-DAG: %[[#f32:]] = OpTypeFloat 32
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; CHECK-DAG: %[[#v4_float:]] = OpTypeVector %[[#f32]] 4
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; CHECK-DAG: %[[#bool:]] = OpTypeBool
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; CHECK-DAG: %[[#v4_bool:]] = OpTypeVector %[[#bool]] 4
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; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3
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; CHECK-LABEL: Begin function test_float
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; CHECK: %[[#fexpr:]] = OpFunctionParameter %[[#f32]]
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; CHECK: %[[#idx1:]] = OpFunctionParameter %[[#uint]]
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define float @test_float(float %fexpr, i32 %idx) {
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entry:
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; CHECK: %[[#fret:]] = OpGroupNonUniformShuffle %[[#f32]] %[[#scope]] %[[#fexpr]] %[[#idx1]]
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%0 = call float @llvm.spv.wave.readlane.f32(float %fexpr, i32 %idx)
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ret float %0
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}
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; CHECK-LABEL: Begin function test_int
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; CHECK: %[[#iexpr:]] = OpFunctionParameter %[[#uint]]
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; CHECK: %[[#idx2:]] = OpFunctionParameter %[[#uint]]
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define i32 @test_int(i32 %iexpr, i32 %idx) {
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entry:
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; CHECK: %[[#iret:]] = OpGroupNonUniformShuffle %[[#uint]] %[[#scope]] %[[#iexpr]] %[[#idx2]]
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%0 = call i32 @llvm.spv.wave.readlane.i32(i32 %iexpr, i32 %idx)
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ret i32 %0
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}
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; CHECK-LABEL: Begin function test_vbool
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; CHECK: %[[#vbexpr:]] = OpFunctionParameter %[[#v4_bool]]
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; CHECK: %[[#idx3:]] = OpFunctionParameter %[[#uint]]
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define <4 x i1> @test_vbool(<4 x i1> %vbexpr, i32 %idx) {
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entry:
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; CHECK: %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_bool]] %[[#scope]] %[[#vbexpr]] %[[#idx3]]
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%0 = call <4 x i1> @llvm.spv.wave.readlane.v4i1(<4 x i1> %vbexpr, i32 %idx)
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ret <4 x i1> %0
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}
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; CHECK-LABEL: Begin function test_vfloat
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; CHECK: %[[#vfexpr:]] = OpFunctionParameter %[[#v4_float]]
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; CHECK: %[[#idx4:]] = OpFunctionParameter %[[#uint]]
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define <4 x float> @test_vfloat(<4 x float> %vfexpr, i32 %idx) {
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entry:
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; CHECK: %[[#vbret:]] = OpGroupNonUniformShuffle %[[#v4_float]] %[[#scope]] %[[#vfexpr]] %[[#idx4]]
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%0 = call <4 x float> @llvm.spv.wave.readlane.v4f32(<4 x float> %vfexpr, i32 %idx)
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ret <4 x float> %0
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}
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declare float @llvm.spv.wave.readlane.f32(float, i32)
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declare i32 @llvm.spv.wave.readlane.i32(i32, i32)
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declare <4 x i1> @llvm.spv.wave.readlane.v4i1(<4 x i1>, i32)
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declare <4 x float> @llvm.spv.wave.readlane.v4f32(<4 x float>, i32)
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