derek.holloway
7502bf64a4
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469 lines
14 KiB
LLVM
469 lines
14 KiB
LLVM
; Test the generated function prologs/epilogs under XPLINK64 on z/OS
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;
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; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z13 | FileCheck --check-prefixes=CHECK64,CHECK %s
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; Test prolog/epilog for non-XPLEAF.
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; Small stack frame.
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; CHECK-LABEL: func0 DS 0H
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; CHECK64: stmg 6,7,1872(4)
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; stmg instruction's displacement field must be 2064-dsa_size
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; as per ABI
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; CHECK64: aghi 4,-192
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; CHECK64: lg 7,2072(4)
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; CHECK64: aghi 4,192
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; CHECK64: b 2(7)
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define void @func0() {
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call i64 (i64) @fun(i64 10)
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ret void
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}
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; Spill all GPR CSRs
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; CHECK-LABEL: func1 DS 0H
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; CHECK64: stmg 6,15,1904(4)
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; CHECK64: aghi 4,-160
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; CHECK64: lmg 7,15,2072(4)
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; CHECK64: aghi 4,160
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; CHECK64: b 2(7)
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define void @func1(ptr %ptr) {
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%l01 = load volatile i64, ptr %ptr
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%l02 = load volatile i64, ptr %ptr
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%l03 = load volatile i64, ptr %ptr
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%l04 = load volatile i64, ptr %ptr
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%l05 = load volatile i64, ptr %ptr
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%l06 = load volatile i64, ptr %ptr
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%l07 = load volatile i64, ptr %ptr
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%l08 = load volatile i64, ptr %ptr
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%l09 = load volatile i64, ptr %ptr
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%l10 = load volatile i64, ptr %ptr
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%l11 = load volatile i64, ptr %ptr
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%l12 = load volatile i64, ptr %ptr
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%l13 = load volatile i64, ptr %ptr
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%l14 = load volatile i64, ptr %ptr
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%l15 = load volatile i64, ptr %ptr
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%add01 = add i64 %l01, %l01
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%add02 = add i64 %l02, %add01
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%add03 = add i64 %l03, %add02
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%add04 = add i64 %l04, %add03
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%add05 = add i64 %l05, %add04
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%add06 = add i64 %l06, %add05
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%add07 = add i64 %l07, %add06
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%add08 = add i64 %l08, %add07
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%add09 = add i64 %l09, %add08
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%add10 = add i64 %l10, %add09
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%add11 = add i64 %l11, %add10
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%add12 = add i64 %l12, %add11
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%add13 = add i64 %l13, %add12
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%add14 = add i64 %l14, %add13
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%add15 = add i64 %l15, %add14
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store volatile i64 %add01, ptr %ptr
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store volatile i64 %add02, ptr %ptr
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store volatile i64 %add03, ptr %ptr
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store volatile i64 %add04, ptr %ptr
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store volatile i64 %add05, ptr %ptr
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store volatile i64 %add06, ptr %ptr
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store volatile i64 %add07, ptr %ptr
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store volatile i64 %add08, ptr %ptr
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store volatile i64 %add09, ptr %ptr
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store volatile i64 %add10, ptr %ptr
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store volatile i64 %add11, ptr %ptr
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store volatile i64 %add12, ptr %ptr
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store volatile i64 %add13, ptr %ptr
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store volatile i64 %add14, ptr %ptr
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store volatile i64 %add15, ptr %ptr
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ret void
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}
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; Spill all FPRs and VRs
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; CHECK-LABEL: func2 DS 0H
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; CHECK64: stmg 6,7,1744(4)
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; CHECK64: aghi 4,-320
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; CHECK64: vst 16,{{[0-9]+}}(4),4
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; CHECK64: vst 17,{{[0-9]+}}(4),4
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; CHECK64: vst 18,{{[0-9]+}}(4),4
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; CHECK64: vst 19,{{[0-9]+}}(4),4
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; CHECK64: vst 20,{{[0-9]+}}(4),4
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; CHECK64: vst 21,{{[0-9]+}}(4),4
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; CHECK64: vst 22,{{[0-9]+}}(4),4
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; CHECK64: vst 23,{{[0-9]+}}(4),4
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; CHECK64: std 8,{{[0-9]+}}(4)
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; CHECK64: std 9,{{[0-9]+}}(4)
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; CHECK64: std 10,{{[0-9]+}}(4)
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; CHECK64: std 11,{{[0-9]+}}(4)
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; CHECK64: std 12,{{[0-9]+}}(4)
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; CHECK64: std 13,{{[0-9]+}}(4)
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; CHECK64: std 14,{{[0-9]+}}(4)
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; CHECK64: std 15,{{[0-9]+}}(4)
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; CHECK64: vl 16,{{[0-9]+}}(4),4
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; CHECK64: vl 17,{{[0-9]+}}(4),4
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; CHECK64: vl 18,{{[0-9]+}}(4),4
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; CHECK64: vl 19,{{[0-9]+}}(4),4
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; CHECK64: vl 20,{{[0-9]+}}(4),4
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; CHECK64: vl 21,{{[0-9]+}}(4),4
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; CHECK64: vl 22,{{[0-9]+}}(4),4
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; CHECK64: vl 23,{{[0-9]+}}(4),4
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; CHECK64: ld 8,{{[0-9]+}}(4)
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; CHECK64: ld 9,{{[0-9]+}}(4)
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; CHECK64: ld 10,{{[0-9]+}}(4)
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; CHECK64: ld 11,{{[0-9]+}}(4)
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; CHECK64: ld 12,{{[0-9]+}}(4)
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; CHECK64: ld 13,{{[0-9]+}}(4)
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; CHECK64: ld 14,{{[0-9]+}}(4)
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; CHECK64: ld 15,{{[0-9]+}}(4)
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; CHECK64: lg 7,2072(4)
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; CHECK64: aghi 4,320
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; CHECK64: b 2(7)
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define void @func2(ptr %ptr, ptr %vec_ptr) {
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%l00 = load volatile double, ptr %ptr
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%l01 = load volatile double, ptr %ptr
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%l02 = load volatile double, ptr %ptr
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%l03 = load volatile double, ptr %ptr
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%l04 = load volatile double, ptr %ptr
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%l05 = load volatile double, ptr %ptr
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%l06 = load volatile double, ptr %ptr
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%l07 = load volatile double, ptr %ptr
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%l08 = load volatile double, ptr %ptr
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%l09 = load volatile double, ptr %ptr
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%l10 = load volatile double, ptr %ptr
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%l11 = load volatile double, ptr %ptr
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%l12 = load volatile double, ptr %ptr
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%l13 = load volatile double, ptr %ptr
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%l14 = load volatile double, ptr %ptr
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%l15 = load volatile double, ptr %ptr
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%add00 = fadd double %l01, %l00
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%add01 = fadd double %l01, %add00
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%add02 = fadd double %l02, %add01
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%add03 = fadd double %l03, %add02
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%add04 = fadd double %l04, %add03
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%add05 = fadd double %l05, %add04
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%add06 = fadd double %l06, %add05
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%add07 = fadd double %l07, %add06
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%add08 = fadd double %l08, %add07
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%add09 = fadd double %l09, %add08
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%add10 = fadd double %l10, %add09
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%add11 = fadd double %l11, %add10
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%add12 = fadd double %l12, %add11
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%add13 = fadd double %l13, %add12
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%add14 = fadd double %l14, %add13
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%add15 = fadd double %l15, %add14
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store volatile double %add00, ptr %ptr
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store volatile double %add01, ptr %ptr
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store volatile double %add02, ptr %ptr
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store volatile double %add03, ptr %ptr
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store volatile double %add04, ptr %ptr
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store volatile double %add05, ptr %ptr
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store volatile double %add06, ptr %ptr
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store volatile double %add07, ptr %ptr
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store volatile double %add08, ptr %ptr
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store volatile double %add09, ptr %ptr
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store volatile double %add10, ptr %ptr
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store volatile double %add11, ptr %ptr
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store volatile double %add12, ptr %ptr
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store volatile double %add13, ptr %ptr
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store volatile double %add14, ptr %ptr
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store volatile double %add15, ptr %ptr
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%v00 = load volatile <2 x i64>, ptr %vec_ptr
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%v01 = load volatile <2 x i64>, ptr %vec_ptr
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%v02 = load volatile <2 x i64>, ptr %vec_ptr
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%v03 = load volatile <2 x i64>, ptr %vec_ptr
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%v04 = load volatile <2 x i64>, ptr %vec_ptr
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%v05 = load volatile <2 x i64>, ptr %vec_ptr
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%v06 = load volatile <2 x i64>, ptr %vec_ptr
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%v07 = load volatile <2 x i64>, ptr %vec_ptr
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%v08 = load volatile <2 x i64>, ptr %vec_ptr
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%v09 = load volatile <2 x i64>, ptr %vec_ptr
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%v10 = load volatile <2 x i64>, ptr %vec_ptr
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%v11 = load volatile <2 x i64>, ptr %vec_ptr
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%v12 = load volatile <2 x i64>, ptr %vec_ptr
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%v13 = load volatile <2 x i64>, ptr %vec_ptr
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%v14 = load volatile <2 x i64>, ptr %vec_ptr
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%v15 = load volatile <2 x i64>, ptr %vec_ptr
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%v16 = load volatile <2 x i64>, ptr %vec_ptr
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%v17 = load volatile <2 x i64>, ptr %vec_ptr
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%v18 = load volatile <2 x i64>, ptr %vec_ptr
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%v19 = load volatile <2 x i64>, ptr %vec_ptr
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%v20 = load volatile <2 x i64>, ptr %vec_ptr
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%v21 = load volatile <2 x i64>, ptr %vec_ptr
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%v22 = load volatile <2 x i64>, ptr %vec_ptr
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%v23 = load volatile <2 x i64>, ptr %vec_ptr
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%v24 = load volatile <2 x i64>, ptr %vec_ptr
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%v25 = load volatile <2 x i64>, ptr %vec_ptr
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%v26 = load volatile <2 x i64>, ptr %vec_ptr
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%v27 = load volatile <2 x i64>, ptr %vec_ptr
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%v28 = load volatile <2 x i64>, ptr %vec_ptr
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%v29 = load volatile <2 x i64>, ptr %vec_ptr
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%v30 = load volatile <2 x i64>, ptr %vec_ptr
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%v31 = load volatile <2 x i64>, ptr %vec_ptr
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%vadd00 = add <2 x i64> %v00, %v00
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%vadd01 = add <2 x i64> %v01, %vadd00
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%vadd02 = add <2 x i64> %v02, %vadd01
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%vadd03 = add <2 x i64> %v03, %vadd02
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%vadd04 = add <2 x i64> %v04, %vadd03
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%vadd05 = add <2 x i64> %v05, %vadd04
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%vadd06 = add <2 x i64> %v06, %vadd05
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%vadd07 = add <2 x i64> %v07, %vadd06
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%vadd08 = add <2 x i64> %v08, %vadd07
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%vadd09 = add <2 x i64> %v09, %vadd08
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%vadd10 = add <2 x i64> %v10, %vadd09
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%vadd11 = add <2 x i64> %v11, %vadd10
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%vadd12 = add <2 x i64> %v12, %vadd11
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%vadd13 = add <2 x i64> %v13, %vadd12
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%vadd14 = add <2 x i64> %v14, %vadd13
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%vadd15 = add <2 x i64> %v15, %vadd14
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%vadd16 = add <2 x i64> %v16, %vadd15
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%vadd17 = add <2 x i64> %v17, %vadd16
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%vadd18 = add <2 x i64> %v18, %vadd17
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%vadd19 = add <2 x i64> %v19, %vadd18
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%vadd20 = add <2 x i64> %v20, %vadd19
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%vadd21 = add <2 x i64> %v21, %vadd20
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%vadd22 = add <2 x i64> %v22, %vadd21
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%vadd23 = add <2 x i64> %v23, %vadd22
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%vadd24 = add <2 x i64> %v24, %vadd23
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%vadd25 = add <2 x i64> %v25, %vadd24
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%vadd26 = add <2 x i64> %v26, %vadd25
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%vadd27 = add <2 x i64> %v27, %vadd26
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%vadd28 = add <2 x i64> %v28, %vadd27
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%vadd29 = add <2 x i64> %v29, %vadd28
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%vadd30 = add <2 x i64> %v30, %vadd29
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%vadd31 = add <2 x i64> %v31, %vadd30
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store volatile <2 x i64> %vadd00, ptr %vec_ptr
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store volatile <2 x i64> %vadd01, ptr %vec_ptr
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store volatile <2 x i64> %vadd02, ptr %vec_ptr
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store volatile <2 x i64> %vadd03, ptr %vec_ptr
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store volatile <2 x i64> %vadd04, ptr %vec_ptr
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store volatile <2 x i64> %vadd05, ptr %vec_ptr
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store volatile <2 x i64> %vadd06, ptr %vec_ptr
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store volatile <2 x i64> %vadd07, ptr %vec_ptr
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store volatile <2 x i64> %vadd08, ptr %vec_ptr
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store volatile <2 x i64> %vadd09, ptr %vec_ptr
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store volatile <2 x i64> %vadd10, ptr %vec_ptr
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store volatile <2 x i64> %vadd11, ptr %vec_ptr
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store volatile <2 x i64> %vadd12, ptr %vec_ptr
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store volatile <2 x i64> %vadd13, ptr %vec_ptr
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store volatile <2 x i64> %vadd14, ptr %vec_ptr
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store volatile <2 x i64> %vadd15, ptr %vec_ptr
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store volatile <2 x i64> %vadd16, ptr %vec_ptr
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store volatile <2 x i64> %vadd17, ptr %vec_ptr
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store volatile <2 x i64> %vadd18, ptr %vec_ptr
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store volatile <2 x i64> %vadd19, ptr %vec_ptr
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store volatile <2 x i64> %vadd20, ptr %vec_ptr
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store volatile <2 x i64> %vadd21, ptr %vec_ptr
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store volatile <2 x i64> %vadd22, ptr %vec_ptr
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store volatile <2 x i64> %vadd23, ptr %vec_ptr
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store volatile <2 x i64> %vadd24, ptr %vec_ptr
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store volatile <2 x i64> %vadd25, ptr %vec_ptr
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store volatile <2 x i64> %vadd26, ptr %vec_ptr
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store volatile <2 x i64> %vadd27, ptr %vec_ptr
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store volatile <2 x i64> %vadd28, ptr %vec_ptr
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store volatile <2 x i64> %vadd29, ptr %vec_ptr
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store volatile <2 x i64> %vadd30, ptr %vec_ptr
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store volatile <2 x i64> %vadd31, ptr %vec_ptr
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ret void
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}
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; Big stack frame, force the use of agfi before stmg
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; despite not requiring stack extension routine.
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; CHECK64: agfi 4,-1040768
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; CHECK64: stmg 6,7,2064(4)
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; CHECK64: agfi 4,1040768
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define void @func3() {
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%arr = alloca [130070 x i64], align 8
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call i64 (ptr) @fun1(ptr %arr)
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ret void
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}
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; Requires the saving of r4 due to variable sized
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; object in stack frame. (Eg: VLA) Sets up frame pointer in r8
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; CHECK64: stmg 4,10,1856(4)
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; CHECK64: aghi 4,-192
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; CHECK64: lg 6,40(5)
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; CHECK64: lg 5,32(5)
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; CHECK64: lgr 8,4
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; CHECK64: basr 7,6
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; CHECK64-NEXT: bcr 0,0
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; CHECK64: lmg 4,10,2048(4)
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define i64 @func4(i64 %n) {
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%vla = alloca i64, i64 %n, align 8
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%call = call i64 @fun2(i64 %n, ptr nonnull %vla, ptr nonnull %vla)
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ret i64 %call
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}
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; Require saving of r4 and in addition, a displacement large enough
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; to force use of agfi before stmg.
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; CHECK64: lgr 0,4
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; CHECK64: agfi 4,-1040224
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; CHECK64: stmg 4,10,2048(4)
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; CHECK64: lgr 8,4
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; CHECK64: basr 7,6
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; CHECK64-NEXT: bcr 0,0
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; CHECK64: lmg 4,10,2048(4)
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define i64 @func5(i64 %n) {
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%vla = alloca i64, i64 %n, align 8
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%arr = alloca [130000 x i64], align 8
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%call = call i64 @fun2(i64 %n, ptr nonnull %vla, ptr %arr)
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ret i64 %call
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}
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; Require saving of r5, which is not restored.
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; CHECK64: stmg 5,9,1864(4)
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; CHECK64-NEXT: aghi 4,-192
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; CHECK64: lmg 7,9,2072(4)
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; CHECK64-NEXT: aghi 4,192
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declare i32 @personality(...)
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declare void @panic()
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define void @func6() uwtable personality ptr @personality {
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entry:
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br label %bb1
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bb1:
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invoke void @panic()
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to label %bb2 unwind label %bb3
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bb2:
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ret void
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bb3:
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%lp = landingpad { ptr, i32 }
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catch ptr null
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br label %bb1
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}
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; CHECK-LABEL: large_stack
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; CHECK64: agfi 4,-1048800
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; CHECK64-NEXT: llgt 3,1208
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; CHECK64-NEXT: cg 4,64(3)
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; CHECK64-NEXT: jhe
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; CHECK64: lg 3,72(3)
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; CHECK64: basr 3,3
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; CHECK64: stmg 6,7,2064(4)
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define void @large_stack0() {
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%arr = alloca [131072 x i64], align 8
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call i64 (ptr) @fun1(ptr %arr)
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ret void
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}
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; CHECK-LABEL: large_stack1 DS 0H
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; CHECK64: agfi 4,-1048800
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; CHECK64: lgr 0,3
|
|
; CHECK64: llgt 3,1208
|
|
; CHECK64: cg 4,64(3)
|
|
; CHECK64: jhe L#BB8_2
|
|
; CHECK64: lg 3,72(3)
|
|
; CHECK64: basr 3,3
|
|
; CHECK64: bcr 0,7
|
|
; CHECK64: L#BB8_2 DS 0H
|
|
; CHECK64: stmg 6,7,2064(4)
|
|
; CHECK64: lgr 3,0
|
|
|
|
define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {
|
|
%arr = alloca [131072 x i64], align 8
|
|
call i64 (ptr, i64, i64, i64) @fun3(ptr %arr,
|
|
i64 %n1, i64 %n2, i64 %n3)
|
|
ret void
|
|
}
|
|
|
|
|
|
; CHECK-LABEL: large_stack2
|
|
; CHECK64: lgr 0,4
|
|
; CHECK64: stg 3,2192(4)
|
|
; CHECK64: agfi 4,-1048800
|
|
; CHECK64: llgt 3,1208
|
|
; CHECK64: cg 4,64(3)
|
|
; CHECK64: jhe L#BB9_2
|
|
; CHECK64: lg 3,72(3)
|
|
; CHECK64: basr 3,3
|
|
; CHECK64: bcr 0,7
|
|
; CHECK64: L#BB9_2 DS 0H
|
|
; CHECK64: lgr 3,0
|
|
; CHECK64: lg 3,2192(3)
|
|
; CHECK64: stmg 4,12,2048(4)
|
|
; CHECK64: lgr 8,4
|
|
define void @large_stack2(i64 %n1, i64 %n2, i64 %n3) {
|
|
%arr0 = alloca [131072 x i64], align 8
|
|
%arr1 = alloca i64, i64 %n1, align 8
|
|
call i64 (ptr, ptr, i64, i64, i64) @fun4(ptr %arr0,
|
|
ptr %arr1, i64 %n1, i64 %n2, i64 %n3)
|
|
ret void
|
|
}
|
|
|
|
; Verify stack alignment is 32
|
|
; CHECK-LABEL: large_stack3
|
|
; CHECK: agfi 4,-2147483648
|
|
; CHECK-NEXT: aghi 4,-224
|
|
; CHECK: agfi 4,2147483616
|
|
; CHECK-NEXT: aghi 4,256
|
|
define void @large_stack3() {
|
|
%arr = alloca [268435457 x i64], align 8
|
|
call i64 (ptr) @fun1(ptr %arr)
|
|
ret void
|
|
}
|
|
|
|
; CHECK-LABEL: L#EPM_leaf_func0_0 DS 0H
|
|
; CHECK: * DSA Size 0x0
|
|
; CHECK: * Entry Flags
|
|
; CHECK: * Bit 1: 1 = Leaf function
|
|
; CHECK: * Bit 2: 0 = Does not use alloca
|
|
; CHECK: DC XL4'00000008'
|
|
; CHECK-LABEL: leaf_func0 DS 0H
|
|
; CHECK-NOT: aghi 4,
|
|
; CHECK-NOT: stmg
|
|
; CHECK: agr 1,2
|
|
; CHECK: msgr 1,3
|
|
; CHECK: aghik 3,1,-4
|
|
; CHECK-NOT: aghi 4,
|
|
; CHECK-NOT: lmg
|
|
; CHECK-LABEL: L#leaf_func0_end_0 DS 0H
|
|
define i64 @leaf_func0(i64 %a, i64 %b, i64 %c) {
|
|
%n = add i64 %a, %b
|
|
%m = mul i64 %n, %c
|
|
%o = sub i64 %m, 4
|
|
ret i64 %o
|
|
}
|
|
|
|
define i64 @named_func(i64 %arg) {
|
|
%sum = add i64 1, %arg
|
|
ret i64 %sum
|
|
}
|
|
|
|
define void @""(ptr %p) {
|
|
call i64 (ptr) @fun1(ptr %p)
|
|
ret void
|
|
}
|
|
|
|
|
|
declare i64 @fun(i64 %arg0)
|
|
declare i64 @fun1(ptr %ptr)
|
|
declare i64 @fun2(i64 %n, ptr %arr0, ptr %arr1)
|
|
declare i64 @fun3(ptr %ptr, i64 %n1, i64 %n2, i64 %n3)
|
|
declare i64 @fun4(ptr %ptr0, ptr %ptr1, i64 %n1, i64 %n2, i64 %n3)
|
|
|
|
; =============================
|
|
; Tests for PPA1 Fields
|
|
; =============================
|
|
|
|
; CHECK64: L#PPA1_func0_0 DS 0H
|
|
; CHECK64: * Length/4 of Parms
|
|
; CHECK64: DC XL2'0000'
|
|
|
|
; CHECK64: L#PPA1_func1_0 DS 0H
|
|
; CHECK64: * Length/4 of Parms
|
|
; CHECK64: DC XL2'0002'
|
|
|
|
; CHECK64: L#PPA1_large_stack1_0 DS 0H
|
|
; CHECK64: * Length/4 of Parms
|
|
; CHECK64: DC XL2'0006'
|
|
|
|
; CHECK-LABEL: L#PPA1_named_func_0 DS 0H
|
|
; CHECK: * PPA1 Flags 4
|
|
; CHECK-NEXT: * Bit 7: 1 = Name Length and Name
|
|
; CHECK-NEXT: DC XL1'81'
|
|
|
|
; CHECK-LABEL: L#PPA1_0 DS 0H
|
|
; CHECK: * PPA1 Flags 4
|
|
; CHECK-NEXT: DC XL1'80'
|