derek.holloway
7502bf64a4
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189 lines
7.0 KiB
LLVM
189 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumb-eabi -mattr=+v6 | FileCheck %s --check-prefixes=THUMBV6
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define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
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; THUMBV6-LABEL: muloti_test:
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; THUMBV6: @ %bb.0: @ %start
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; THUMBV6-NEXT: .save {r4, r5, r6, r7, lr}
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; THUMBV6-NEXT: push {r4, r5, r6, r7, lr}
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; THUMBV6-NEXT: .pad #60
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; THUMBV6-NEXT: sub sp, #60
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; THUMBV6-NEXT: mov r6, r3
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; THUMBV6-NEXT: mov r1, r2
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; THUMBV6-NEXT: str r2, [sp, #36] @ 4-byte Spill
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; THUMBV6-NEXT: mov r4, r0
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; THUMBV6-NEXT: str r0, [sp, #48] @ 4-byte Spill
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; THUMBV6-NEXT: ldr r2, [sp, #88]
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; THUMBV6-NEXT: str r2, [sp, #56] @ 4-byte Spill
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; THUMBV6-NEXT: movs r5, #0
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; THUMBV6-NEXT: mov r0, r1
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: str r1, [sp, #28] @ 4-byte Spill
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; THUMBV6-NEXT: str r0, [r4]
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; THUMBV6-NEXT: ldr r2, [sp, #96]
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; THUMBV6-NEXT: str r2, [sp, #40] @ 4-byte Spill
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; THUMBV6-NEXT: mov r4, r6
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; THUMBV6-NEXT: str r6, [sp, #44] @ 4-byte Spill
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; THUMBV6-NEXT: mov r0, r6
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: str r0, [sp, #52] @ 4-byte Spill
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; THUMBV6-NEXT: mov r7, r1
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; THUMBV6-NEXT: subs r0, r1, #1
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; THUMBV6-NEXT: sbcs r7, r0
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; THUMBV6-NEXT: ldr r0, [sp, #100]
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; THUMBV6-NEXT: str r0, [sp, #32] @ 4-byte Spill
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: ldr r6, [sp, #36] @ 4-byte Reload
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; THUMBV6-NEXT: mov r2, r6
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: str r0, [sp, #24] @ 4-byte Spill
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; THUMBV6-NEXT: subs r2, r1, #1
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; THUMBV6-NEXT: sbcs r1, r2
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; THUMBV6-NEXT: subs r2, r4, #1
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; THUMBV6-NEXT: mov r3, r4
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; THUMBV6-NEXT: sbcs r3, r2
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; THUMBV6-NEXT: ldr r4, [sp, #32] @ 4-byte Reload
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; THUMBV6-NEXT: subs r2, r4, #1
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; THUMBV6-NEXT: sbcs r4, r2
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; THUMBV6-NEXT: ands r4, r3
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; THUMBV6-NEXT: orrs r4, r1
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; THUMBV6-NEXT: orrs r4, r7
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; THUMBV6-NEXT: ldr r0, [sp, #52] @ 4-byte Reload
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; THUMBV6-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
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; THUMBV6-NEXT: adds r7, r1, r0
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; THUMBV6-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: mov r2, r6
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: str r0, [sp, #24] @ 4-byte Spill
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; THUMBV6-NEXT: adds r0, r1, r7
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; THUMBV6-NEXT: str r0, [sp, #20] @ 4-byte Spill
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; THUMBV6-NEXT: mov r0, r5
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; THUMBV6-NEXT: adcs r0, r5
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; THUMBV6-NEXT: orrs r0, r4
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; THUMBV6-NEXT: str r0, [sp, #16] @ 4-byte Spill
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; THUMBV6-NEXT: ldr r0, [sp, #92]
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; THUMBV6-NEXT: str r0, [sp, #52] @ 4-byte Spill
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; THUMBV6-NEXT: ldr r7, [sp, #80]
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: mov r2, r7
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; THUMBV6-NEXT: mov r4, r1
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; THUMBV6-NEXT: subs r0, r1, #1
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; THUMBV6-NEXT: sbcs r4, r0
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; THUMBV6-NEXT: ldr r6, [sp, #84]
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; THUMBV6-NEXT: mov r0, r6
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: ldr r2, [sp, #56] @ 4-byte Reload
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: str r0, [sp, #4] @ 4-byte Spill
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; THUMBV6-NEXT: subs r2, r1, #1
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; THUMBV6-NEXT: sbcs r1, r2
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; THUMBV6-NEXT: ldr r3, [sp, #52] @ 4-byte Reload
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; THUMBV6-NEXT: subs r2, r3, #1
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; THUMBV6-NEXT: sbcs r3, r2
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; THUMBV6-NEXT: str r6, [sp, #8] @ 4-byte Spill
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; THUMBV6-NEXT: subs r2, r6, #1
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; THUMBV6-NEXT: sbcs r6, r2
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; THUMBV6-NEXT: ands r6, r3
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; THUMBV6-NEXT: orrs r6, r1
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; THUMBV6-NEXT: orrs r6, r4
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; THUMBV6-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; THUMBV6-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
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; THUMBV6-NEXT: adds r4, r1, r0
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; THUMBV6-NEXT: mov r0, r7
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: ldr r2, [sp, #56] @ 4-byte Reload
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: adds r4, r1, r4
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: adcs r1, r5
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; THUMBV6-NEXT: orrs r1, r6
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; THUMBV6-NEXT: ldr r3, [sp, #40] @ 4-byte Reload
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; THUMBV6-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
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; THUMBV6-NEXT: orrs r3, r2
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; THUMBV6-NEXT: subs r2, r3, #1
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; THUMBV6-NEXT: sbcs r3, r2
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; THUMBV6-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
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; THUMBV6-NEXT: orrs r7, r2
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; THUMBV6-NEXT: subs r2, r7, #1
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; THUMBV6-NEXT: sbcs r7, r2
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; THUMBV6-NEXT: ands r7, r3
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; THUMBV6-NEXT: orrs r7, r1
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; THUMBV6-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
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; THUMBV6-NEXT: orrs r7, r1
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; THUMBV6-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
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; THUMBV6-NEXT: adds r0, r0, r1
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; THUMBV6-NEXT: str r0, [sp, #40] @ 4-byte Spill
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; THUMBV6-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
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; THUMBV6-NEXT: adcs r4, r0
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; THUMBV6-NEXT: str r4, [sp, #32] @ 4-byte Spill
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; THUMBV6-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: ldr r2, [sp, #56] @ 4-byte Reload
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: mov r4, r1
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; THUMBV6-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
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; THUMBV6-NEXT: adds r6, r0, r1
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; THUMBV6-NEXT: adcs r4, r5
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; THUMBV6-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: ldr r2, [sp, #52] @ 4-byte Reload
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: adds r0, r0, r6
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; THUMBV6-NEXT: ldr r2, [sp, #48] @ 4-byte Reload
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; THUMBV6-NEXT: str r0, [r2, #4]
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; THUMBV6-NEXT: adcs r1, r5
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; THUMBV6-NEXT: adds r4, r4, r1
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; THUMBV6-NEXT: mov r6, r5
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; THUMBV6-NEXT: adcs r6, r5
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; THUMBV6-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
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; THUMBV6-NEXT: mov r1, r5
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; THUMBV6-NEXT: ldr r2, [sp, #52] @ 4-byte Reload
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; THUMBV6-NEXT: mov r3, r5
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; THUMBV6-NEXT: bl __aeabi_lmul
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; THUMBV6-NEXT: adds r0, r0, r4
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; THUMBV6-NEXT: adcs r1, r6
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; THUMBV6-NEXT: ldr r2, [sp, #40] @ 4-byte Reload
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; THUMBV6-NEXT: adds r0, r0, r2
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; THUMBV6-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
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; THUMBV6-NEXT: adcs r1, r2
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; THUMBV6-NEXT: ldr r2, [sp, #48] @ 4-byte Reload
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; THUMBV6-NEXT: str r0, [r2, #8]
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; THUMBV6-NEXT: str r1, [r2, #12]
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; THUMBV6-NEXT: adcs r5, r5
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; THUMBV6-NEXT: orrs r5, r7
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; THUMBV6-NEXT: movs r0, #1
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; THUMBV6-NEXT: ands r0, r5
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; THUMBV6-NEXT: strb r0, [r2, #16]
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; THUMBV6-NEXT: add sp, #60
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; THUMBV6-NEXT: pop {r4, r5, r6, r7, pc}
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start:
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%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
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%1 = extractvalue { i128, i1 } %0, 0
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%2 = extractvalue { i128, i1 } %0, 1
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%3 = zext i1 %2 to i8
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%4 = insertvalue { i128, i8 } undef, i128 %1, 0
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%5 = insertvalue { i128, i8 } %4, i8 %3, 1
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ret { i128, i8 } %5
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}
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; Function Attrs: nounwind readnone speculatable
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declare { i128, i1 } @llvm.umul.with.overflow.i128(i128, i128) #1
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attributes #0 = { nounwind readnone uwtable }
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attributes #1 = { nounwind readnone speculatable }
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attributes #2 = { nounwind }
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