derek.holloway
7502bf64a4
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51 lines
2.0 KiB
LLVM
51 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc %s -o - | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7em-arm-none-eabi"
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%struct.a = type { i32, ptr, i8, i8, i8, i8, ptr, ptr, i16, i16, i16, i16, i16, i16, i16, i16, i32, i32, i32, i32, i32, i32, i32 }
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%struct.b = type { i8, i8, i8, i8, i32, i16, i16, i32, i32, i32, i32, [16 x i8], [64 x i8], [128 x i8], i32, [68 x i8] }
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define void @test(ptr nocapture %dhcp, i16 zeroext %value) #0 {
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; CHECK-LABEL: test:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldrh r2, [r0, #20]
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; CHECK-NEXT: adds r3, r2, #1
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; CHECK-NEXT: strh r3, [r0, #20]
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; CHECK-NEXT: ldr r3, [r0, #16]
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; CHECK-NEXT: add r2, r3
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; CHECK-NEXT: lsrs r3, r1, #8
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; CHECK-NEXT: strb.w r3, [r2, #240]
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; CHECK-NEXT: ldrh r2, [r0, #20]
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; CHECK-NEXT: adds r3, r2, #1
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; CHECK-NEXT: strh r3, [r0, #20]
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; CHECK-NEXT: ldr r0, [r0, #16]
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; CHECK-NEXT: add r0, r2
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; CHECK-NEXT: strb.w r1, [r0, #240]
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; CHECK-NEXT: bx lr
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entry:
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%shr = lshr i16 %value, 8
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%conv1 = trunc i16 %shr to i8
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%msg_out = getelementptr inbounds %struct.a, ptr %dhcp, i32 0, i32 7
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%0 = load ptr, ptr %msg_out, align 4
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%options_out_len = getelementptr inbounds %struct.a, ptr %dhcp, i32 0, i32 8
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%1 = load i16, ptr %options_out_len, align 4
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%inc = add i16 %1, 1
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store i16 %inc, ptr %options_out_len, align 4
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%idxprom = zext i16 %1 to i32
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%arrayidx = getelementptr inbounds %struct.b, ptr %0, i32 0, i32 15, i32 %idxprom
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store i8 %conv1, ptr %arrayidx, align 1
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%conv4 = trunc i16 %value to i8
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%2 = load ptr, ptr %msg_out, align 4
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%3 = load i16, ptr %options_out_len, align 4
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%inc8 = add i16 %3, 1
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store i16 %inc8, ptr %options_out_len, align 4
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%idxprom9 = zext i16 %3 to i32
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%arrayidx10 = getelementptr inbounds %struct.b, ptr %2, i32 0, i32 15, i32 %idxprom9
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store i8 %conv4, ptr %arrayidx10, align 1
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ret void
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}
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attributes #0 = { minsize optsize "target-cpu"="cortex-m4" }
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