derek.holloway
7502bf64a4
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123 lines
6.4 KiB
LLVM
123 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s --mattr=+mve.fp -o - | FileCheck %s
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target triple = "thumbv8.1m.main-none-none-eabi"
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; Expected to not transform
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define arm_aapcs_vfpcc <2 x half> @complex_add_v2f16(<2 x half> %a, <2 x half> %b) {
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; CHECK-LABEL: complex_add_v2f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovx.f16 s2, s4
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; CHECK-NEXT: vadd.f16 s2, s2, s0
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; CHECK-NEXT: vmovx.f16 s0, s0
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; CHECK-NEXT: vsub.f16 s0, s4, s0
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; CHECK-NEXT: vins.f16 s0, s2
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <2 x half> %a, <2 x half> zeroinitializer, <1 x i32> <i32 0>
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%a.imag = shufflevector <2 x half> %a, <2 x half> zeroinitializer, <1 x i32> <i32 1>
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%b.real = shufflevector <2 x half> %b, <2 x half> zeroinitializer, <1 x i32> <i32 0>
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%b.imag = shufflevector <2 x half> %b, <2 x half> zeroinitializer, <1 x i32> <i32 1>
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%0 = fsub fast <1 x half> %b.real, %a.imag
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%1 = fadd fast <1 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <1 x half> %0, <1 x half> %1, <2 x i32> <i32 0, i32 1>
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ret <2 x half> %interleaved.vec
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}
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; Expected to not transform
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define arm_aapcs_vfpcc <4 x half> @complex_add_v4f16(<4 x half> %a, <4 x half> %b) {
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; CHECK-LABEL: complex_add_v4f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovx.f16 s12, s4
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; CHECK-NEXT: vmovx.f16 s2, s5
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; CHECK-NEXT: vmovx.f16 s8, s0
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; CHECK-NEXT: vins.f16 s12, s2
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; CHECK-NEXT: vmovx.f16 s2, s1
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; CHECK-NEXT: vins.f16 s0, s1
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; CHECK-NEXT: vins.f16 s8, s2
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; CHECK-NEXT: vins.f16 s4, s5
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; CHECK-NEXT: vadd.f16 q3, q3, q0
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; CHECK-NEXT: vsub.f16 q0, q1, q2
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; CHECK-NEXT: vmovx.f16 s1, s0
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; CHECK-NEXT: vmovx.f16 s2, s12
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; CHECK-NEXT: vins.f16 s0, s12
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; CHECK-NEXT: vins.f16 s1, s2
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%a.imag = shufflevector <4 x half> %a, <4 x half> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%b.real = shufflevector <4 x half> %b, <4 x half> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%b.imag = shufflevector <4 x half> %b, <4 x half> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%0 = fsub fast <2 x half> %b.real, %a.imag
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%1 = fadd fast <2 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <2 x half> %0, <2 x half> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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ret <4 x half> %interleaved.vec
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}
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; Expected to transform
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define arm_aapcs_vfpcc <8 x half> @complex_add_v8f16(<8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: complex_add_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcadd.f16 q0, q1, q0, #90
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <8 x half> %a, <8 x half> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%a.imag = shufflevector <8 x half> %a, <8 x half> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%b.real = shufflevector <8 x half> %b, <8 x half> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b.imag = shufflevector <8 x half> %b, <8 x half> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%0 = fsub fast <4 x half> %b.real, %a.imag
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%1 = fadd fast <4 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <4 x half> %0, <4 x half> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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ret <8 x half> %interleaved.vec
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}
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; Expected to transform
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define arm_aapcs_vfpcc <16 x half> @complex_add_v16f16(<16 x half> %a, <16 x half> %b) {
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; CHECK-LABEL: complex_add_v16f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcadd.f16 q0, q2, q0, #90
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; CHECK-NEXT: vcadd.f16 q1, q3, q1, #90
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <16 x half> %a, <16 x half> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%a.imag = shufflevector <16 x half> %a, <16 x half> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%b.real = shufflevector <16 x half> %b, <16 x half> zeroinitializer, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%b.imag = shufflevector <16 x half> %b, <16 x half> zeroinitializer, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%0 = fsub fast <8 x half> %b.real, %a.imag
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%1 = fadd fast <8 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <8 x half> %0, <8 x half> %1, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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ret <16 x half> %interleaved.vec
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}
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; Expected to transform
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define arm_aapcs_vfpcc <32 x half> @complex_add_v32f16(<32 x half> %a, <32 x half> %b) {
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; CHECK-LABEL: complex_add_v32f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: add r0, sp, #16
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; CHECK-NEXT: vldrw.u32 q4, [r0]
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; CHECK-NEXT: add r0, sp, #32
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; CHECK-NEXT: vcadd.f16 q0, q4, q0, #90
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; CHECK-NEXT: vldrw.u32 q4, [r0]
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; CHECK-NEXT: add r0, sp, #48
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; CHECK-NEXT: vcadd.f16 q1, q4, q1, #90
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; CHECK-NEXT: vldrw.u32 q4, [r0]
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; CHECK-NEXT: add r0, sp, #64
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; CHECK-NEXT: vcadd.f16 q2, q4, q2, #90
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; CHECK-NEXT: vldrw.u32 q4, [r0]
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; CHECK-NEXT: vcadd.f16 q3, q4, q3, #90
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <32 x half> %a, <32 x half> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%a.imag = shufflevector <32 x half> %a, <32 x half> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%b.real = shufflevector <32 x half> %b, <32 x half> zeroinitializer, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%b.imag = shufflevector <32 x half> %b, <32 x half> zeroinitializer, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%0 = fsub fast <16 x half> %b.real, %a.imag
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%1 = fadd fast <16 x half> %b.imag, %a.real
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%interleaved.vec = shufflevector <16 x half> %0, <16 x half> %1, <32 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23, i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
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ret <32 x half> %interleaved.vec
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}
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