derek.holloway
7502bf64a4
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125 lines
5.7 KiB
LLVM
125 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s --mattr=+mve.fp -o - | FileCheck %s
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target triple = "thumbv8.1m.main-none-none-eabi"
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; Expected to not transform
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define arm_aapcs_vfpcc <2 x float> @complex_mul_v2f32(<2 x float> %a, <2 x float> %b) {
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; CHECK-LABEL: complex_mul_v2f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmul.f32 s9, s5, s0
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; CHECK-NEXT: vmul.f32 s8, s1, s5
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; CHECK-NEXT: vfma.f32 s9, s4, s1
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; CHECK-NEXT: vfnms.f32 s8, s4, s0
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; CHECK-NEXT: vmov q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <2 x float> %a, <2 x float> poison, <1 x i32> <i32 0>
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%a.imag = shufflevector <2 x float> %a, <2 x float> poison, <1 x i32> <i32 1>
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%b.real = shufflevector <2 x float> %b, <2 x float> poison, <1 x i32> <i32 0>
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%b.imag = shufflevector <2 x float> %b, <2 x float> poison, <1 x i32> <i32 1>
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%0 = fmul fast <1 x float> %b.imag, %a.real
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%1 = fmul fast <1 x float> %b.real, %a.imag
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%2 = fadd fast <1 x float> %1, %0
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%3 = fmul fast <1 x float> %b.real, %a.real
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%4 = fmul fast <1 x float> %a.imag, %b.imag
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%5 = fsub fast <1 x float> %3, %4
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%interleaved.vec = shufflevector <1 x float> %5, <1 x float> %2, <2 x i32> <i32 0, i32 1>
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ret <2 x float> %interleaved.vec
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}
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; Expected to transform
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define arm_aapcs_vfpcc <4 x float> @complex_mul_v4f32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: complex_mul_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcmul.f32 q2, q0, q1, #0
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; CHECK-NEXT: vcmla.f32 q2, q0, q1, #90
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; CHECK-NEXT: vmov q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 0, i32 2>
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%a.imag = shufflevector <4 x float> %a, <4 x float> poison, <2 x i32> <i32 1, i32 3>
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%b.real = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 0, i32 2>
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%b.imag = shufflevector <4 x float> %b, <4 x float> poison, <2 x i32> <i32 1, i32 3>
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%0 = fmul fast <2 x float> %b.imag, %a.real
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%1 = fmul fast <2 x float> %b.real, %a.imag
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%2 = fadd fast <2 x float> %1, %0
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%3 = fmul fast <2 x float> %b.real, %a.real
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%4 = fmul fast <2 x float> %a.imag, %b.imag
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%5 = fsub fast <2 x float> %3, %4
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%interleaved.vec = shufflevector <2 x float> %5, <2 x float> %2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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ret <4 x float> %interleaved.vec
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}
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; Expected to transform
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define arm_aapcs_vfpcc <8 x float> @complex_mul_v8f32(<8 x float> %a, <8 x float> %b) {
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; CHECK-LABEL: complex_mul_v8f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vcmul.f32 q4, q0, q2, #0
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; CHECK-NEXT: vcmla.f32 q4, q0, q2, #90
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; CHECK-NEXT: vcmul.f32 q2, q1, q3, #0
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; CHECK-NEXT: vcmla.f32 q2, q1, q3, #90
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; CHECK-NEXT: vmov q0, q4
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; CHECK-NEXT: vmov q1, q2
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%a.imag = shufflevector <8 x float> %a, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%b.real = shufflevector <8 x float> %b, <8 x float> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b.imag = shufflevector <8 x float> %b, <8 x float> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%0 = fmul fast <4 x float> %b.imag, %a.real
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%1 = fmul fast <4 x float> %b.real, %a.imag
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%2 = fadd fast <4 x float> %1, %0
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%3 = fmul fast <4 x float> %b.real, %a.real
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%4 = fmul fast <4 x float> %a.imag, %b.imag
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%5 = fsub fast <4 x float> %3, %4
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%interleaved.vec = shufflevector <4 x float> %5, <4 x float> %2, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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ret <8 x float> %interleaved.vec
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}
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; Expected to transform
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define arm_aapcs_vfpcc <16 x float> @complex_mul_v16f32(<16 x float> %a, <16 x float> %b) {
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; CHECK-LABEL: complex_mul_v16f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: add r3, sp, #64
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; CHECK-NEXT: add r2, sp, #80
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; CHECK-NEXT: vldrw.u32 q5, [r3]
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; CHECK-NEXT: add r1, sp, #96
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; CHECK-NEXT: add r0, sp, #112
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; CHECK-NEXT: vcmul.f32 q4, q0, q5, #0
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; CHECK-NEXT: vcmla.f32 q4, q0, q5, #90
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; CHECK-NEXT: vldrw.u32 q0, [r2]
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; CHECK-NEXT: vcmul.f32 q5, q1, q0, #0
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; CHECK-NEXT: vcmla.f32 q5, q1, q0, #90
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vmov q1, q5
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; CHECK-NEXT: vcmul.f32 q6, q2, q0, #0
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; CHECK-NEXT: vcmla.f32 q6, q2, q0, #90
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vmov q2, q6
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; CHECK-NEXT: vcmul.f32 q7, q3, q0, #0
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; CHECK-NEXT: vcmla.f32 q7, q3, q0, #90
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; CHECK-NEXT: vmov q0, q4
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; CHECK-NEXT: vmov q3, q7
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECK-NEXT: bx lr
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entry:
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%a.real = shufflevector <16 x float> %a, <16 x float> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%a.imag = shufflevector <16 x float> %a, <16 x float> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%b.real = shufflevector <16 x float> %b, <16 x float> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%b.imag = shufflevector <16 x float> %b, <16 x float> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%0 = fmul fast <8 x float> %b.imag, %a.real
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%1 = fmul fast <8 x float> %b.real, %a.imag
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%2 = fadd fast <8 x float> %1, %0
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%3 = fmul fast <8 x float> %b.real, %a.real
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%4 = fmul fast <8 x float> %a.imag, %b.imag
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%5 = fsub fast <8 x float> %3, %4
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%interleaved.vec = shufflevector <8 x float> %5, <8 x float> %2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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ret <16 x float> %interleaved.vec
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}
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