derek.holloway
7502bf64a4
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165 lines
6.4 KiB
LLVM
165 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s --mattr=+mve -o - --verify-machineinstrs | FileCheck %s
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target triple = "thumbv8.1m.main-none-none-eabi"
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; Expected to not transform
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define arm_aapcs_vfpcc <2 x i64> @complex_add_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: complex_add_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: vmov r0, r1, d0
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; CHECK-NEXT: vmov r2, r3, d3
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; CHECK-NEXT: adds.w lr, r2, r0
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; CHECK-NEXT: adc.w r12, r3, r1
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; CHECK-NEXT: vmov r2, r3, d1
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; CHECK-NEXT: vmov r1, r0, d2
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; CHECK-NEXT: subs r1, r1, r2
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; CHECK-NEXT: vmov q0[2], q0[0], r1, lr
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; CHECK-NEXT: sbcs r0, r3
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; CHECK-NEXT: vmov q0[3], q0[1], r0, r12
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%a.real = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <1 x i32> <i32 0>
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%a.imag = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <1 x i32> <i32 1>
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%b.real = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <1 x i32> <i32 0>
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%b.imag = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <1 x i32> <i32 1>
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%0 = sub <1 x i64> %b.real, %a.imag
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%1 = add <1 x i64> %b.imag, %a.real
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%interleaved.vec = shufflevector <1 x i64> %0, <1 x i64> %1, <2 x i32> <i32 0, i32 1>
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ret <2 x i64> %interleaved.vec
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}
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; Expected to not transform
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define arm_aapcs_vfpcc <4 x i64> @complex_add_v4i64(<4 x i64> %a, <4 x i64> %b) {
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; CHECK-LABEL: complex_add_v4i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .vsave {d8, d9}
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; CHECK-NEXT: vpush {d8, d9}
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; CHECK-NEXT: vmov q4, q1
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; CHECK-NEXT: vmov r2, r3, d7
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; CHECK-NEXT: vmov r0, r1, d8
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; CHECK-NEXT: adds.w lr, r2, r0
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; CHECK-NEXT: adc.w r12, r3, r1
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; CHECK-NEXT: vmov r2, r3, d0
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; CHECK-NEXT: vmov r1, r0, d5
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; CHECK-NEXT: adds r1, r1, r2
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; CHECK-NEXT: adcs r0, r3
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; CHECK-NEXT: vmov q1[2], q1[0], r1, lr
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; CHECK-NEXT: vmov q1[3], q1[1], r0, r12
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; CHECK-NEXT: vmov r0, r1, d9
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; CHECK-NEXT: vmov r2, r3, d6
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; CHECK-NEXT: subs.w lr, r2, r0
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; CHECK-NEXT: sbc.w r12, r3, r1
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; CHECK-NEXT: vmov r2, r3, d1
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; CHECK-NEXT: vmov r1, r0, d4
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; CHECK-NEXT: vmov.f32 s2, s4
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; CHECK-NEXT: vmov.f32 s3, s5
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; CHECK-NEXT: subs r1, r1, r2
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; CHECK-NEXT: vmov q2[2], q2[0], r1, lr
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; CHECK-NEXT: sbcs r0, r3
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; CHECK-NEXT: vmov q2[3], q2[1], r0, r12
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; CHECK-NEXT: vmov.f32 s0, s8
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; CHECK-NEXT: vmov.f32 s4, s10
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; CHECK-NEXT: vmov.f32 s1, s9
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; CHECK-NEXT: vmov.f32 s5, s11
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; CHECK-NEXT: vpop {d8, d9}
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%a.real = shufflevector <4 x i64> %a, <4 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%a.imag = shufflevector <4 x i64> %a, <4 x i64> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%b.real = shufflevector <4 x i64> %b, <4 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%b.imag = shufflevector <4 x i64> %b, <4 x i64> zeroinitializer, <2 x i32> <i32 1, i32 3>
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%0 = sub <2 x i64> %b.real, %a.imag
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%1 = add <2 x i64> %b.imag, %a.real
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%interleaved.vec = shufflevector <2 x i64> %0, <2 x i64> %1, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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ret <4 x i64> %interleaved.vec
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}
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; Expected to not transform
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define arm_aapcs_vfpcc <8 x i64> @complex_add_v8i64(<8 x i64> %a, <8 x i64> %b) {
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; CHECK-LABEL: complex_add_v8i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: add r2, sp, #72
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; CHECK-NEXT: vmov q4, q1
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; CHECK-NEXT: vldrw.u32 q5, [r2]
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; CHECK-NEXT: vmov r0, r1, d8
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; CHECK-NEXT: vmov r2, r3, d11
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; CHECK-NEXT: adds.w lr, r2, r0
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; CHECK-NEXT: adc.w r12, r3, r1
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; CHECK-NEXT: add r1, sp, #56
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; CHECK-NEXT: vldrw.u32 q6, [r1]
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; CHECK-NEXT: vmov r2, r3, d0
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; CHECK-NEXT: vmov r1, r0, d13
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; CHECK-NEXT: adds r1, r1, r2
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; CHECK-NEXT: adcs r0, r3
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; CHECK-NEXT: vmov q1[2], q1[0], r1, lr
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; CHECK-NEXT: vmov q1[3], q1[1], r0, r12
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; CHECK-NEXT: vmov r0, r1, d9
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; CHECK-NEXT: vmov r2, r3, d10
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; CHECK-NEXT: subs.w lr, r2, r0
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; CHECK-NEXT: sbc.w r12, r3, r1
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; CHECK-NEXT: vmov r2, r3, d1
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; CHECK-NEXT: vmov r1, r0, d12
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; CHECK-NEXT: vmov.f32 s2, s4
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; CHECK-NEXT: vmov.f32 s3, s5
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; CHECK-NEXT: subs r1, r1, r2
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; CHECK-NEXT: add r2, sp, #104
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; CHECK-NEXT: vldrw.u32 q5, [r2]
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; CHECK-NEXT: sbcs r0, r3
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; CHECK-NEXT: vmov q4[2], q4[0], r1, lr
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; CHECK-NEXT: vmov q4[3], q4[1], r0, r12
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; CHECK-NEXT: vmov r0, r1, d6
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; CHECK-NEXT: vmov r2, r3, d11
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; CHECK-NEXT: vmov.f32 s0, s16
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; CHECK-NEXT: vmov.f32 s4, s18
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; CHECK-NEXT: vmov.f32 s1, s17
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; CHECK-NEXT: vmov.f32 s5, s19
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; CHECK-NEXT: adds.w lr, r2, r0
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; CHECK-NEXT: adc.w r12, r3, r1
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; CHECK-NEXT: add r1, sp, #88
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; CHECK-NEXT: vldrw.u32 q6, [r1]
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; CHECK-NEXT: vmov r2, r3, d4
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; CHECK-NEXT: vmov r1, r0, d13
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; CHECK-NEXT: adds r1, r1, r2
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; CHECK-NEXT: adcs r0, r3
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; CHECK-NEXT: vmov q4[2], q4[0], r1, lr
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; CHECK-NEXT: vmov q4[3], q4[1], r0, r12
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; CHECK-NEXT: vmov r0, r1, d7
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; CHECK-NEXT: vmov r2, r3, d10
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; CHECK-NEXT: subs.w lr, r2, r0
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; CHECK-NEXT: sbc.w r12, r3, r1
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; CHECK-NEXT: vmov r2, r3, d5
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; CHECK-NEXT: vmov r1, r0, d12
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; CHECK-NEXT: vmov.f32 s10, s16
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; CHECK-NEXT: vmov.f32 s11, s17
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; CHECK-NEXT: subs r1, r1, r2
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; CHECK-NEXT: vmov q3[2], q3[0], r1, lr
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; CHECK-NEXT: sbcs r0, r3
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; CHECK-NEXT: vmov q3[3], q3[1], r0, r12
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; CHECK-NEXT: vmov.f32 s16, s14
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; CHECK-NEXT: vmov.f32 s8, s12
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; CHECK-NEXT: vmov.f32 s17, s15
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; CHECK-NEXT: vmov.f32 s9, s13
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; CHECK-NEXT: vmov q3, q4
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; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%a.real = shufflevector <8 x i64> %a, <8 x i64> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%a.imag = shufflevector <8 x i64> %a, <8 x i64> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%b.real = shufflevector <8 x i64> %b, <8 x i64> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b.imag = shufflevector <8 x i64> %b, <8 x i64> zeroinitializer, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%0 = sub <4 x i64> %b.real, %a.imag
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%1 = add <4 x i64> %b.imag, %a.real
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%interleaved.vec = shufflevector <4 x i64> %0, <4 x i64> %1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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ret <8 x i64> %interleaved.vec
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}
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