derek.holloway
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109 lines
3.7 KiB
LLVM
109 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
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define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {
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; CHECK-MVE-LABEL: fneg_float16_t:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vmov.i16 q1, #0x8000
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; CHECK-MVE-NEXT: veor q0, q0, q1
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-MVEFP-LABEL: fneg_float16_t:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vneg.f16 q0, q0
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) {
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; CHECK-MVE-LABEL: fneg_float32_t:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vmov.i32 q1, #0x80000000
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; CHECK-MVE-NEXT: veor q0, q0, q1
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-MVEFP-LABEL: fneg_float32_t:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vneg.f32 q0, q0
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = fsub nnan ninf nsz <4 x float> <float 0.0e0, float 0.0e0, float 0.0e0, float 0.0e0>, %src
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ret <4 x float> %0
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}
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define arm_aapcs_vfpcc <2 x double> @fneg_float64_t(<2 x double> %src) {
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; CHECK-LABEL: fneg_float64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: adr r0, .LCPI2_0
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: veor q0, q0, q1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI2_0:
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 2147483648 @ 0x80000000
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 2147483648 @ 0x80000000
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entry:
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%0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src
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ret <2 x double> %0
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}
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define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
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; CHECK-MVE-LABEL: fabs_float16_t:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vbic.i16 q0, #0x8000
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-MVEFP-LABEL: fabs_float16_t:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vabs.f16 q0, q0
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src)
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {
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; CHECK-MVE-LABEL: fabs_float32_t:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vbic.i32 q0, #0x80000000
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-MVEFP-LABEL: fabs_float32_t:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vabs.f32 q0, q0
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = call nnan ninf nsz <4 x float> @llvm.fabs.v4f32(<4 x float> %src)
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ret <4 x float> %0
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}
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define arm_aapcs_vfpcc <2 x double> @fabs_float64_t(<2 x double> %src) {
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; CHECK-LABEL: fabs_float64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: adr r0, .LCPI5_0
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vand q0, q0, q1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI5_0:
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
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; CHECK-NEXT: .long 4294967295 @ 0xffffffff
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; CHECK-NEXT: .long 2147483647 @ 0x7fffffff
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entry:
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%0 = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> %src)
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ret <2 x double> %0
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}
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
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declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
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declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
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