derek.holloway
7502bf64a4
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310 lines
11 KiB
LLVM
310 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <16 x i8> @sadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
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; CHECK-LABEL: sadd_int8_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqadd.s8 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @sadd_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: sadd_int16_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqadd.s16 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @sadd_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LABEL: sadd_int32_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqadd.s32 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @sadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
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; CHECK-LABEL: sadd_int64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, lr}
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; CHECK-NEXT: push {r4, r5, r6, lr}
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; CHECK-NEXT: vmov r0, r1, d2
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; CHECK-NEXT: vmov r2, r3, d0
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; CHECK-NEXT: vmov r4, r5, d1
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; CHECK-NEXT: adds.w r12, r2, r0
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; CHECK-NEXT: adc.w r0, r3, r1
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; CHECK-NEXT: subs.w r2, r12, r2
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; CHECK-NEXT: sbcs.w r2, r0, r3
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; CHECK-NEXT: mov.w r3, #0
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; CHECK-NEXT: cset r2, lt
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; CHECK-NEXT: cmp.w r3, r1, lsr #31
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; CHECK-NEXT: it ne
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; CHECK-NEXT: eorne r2, r2, #1
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; CHECK-NEXT: rsb.w lr, r2, #0
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; CHECK-NEXT: vmov r2, r1, d3
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; CHECK-NEXT: adds r2, r2, r4
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; CHECK-NEXT: adc.w r6, r5, r1
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; CHECK-NEXT: subs r4, r2, r4
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; CHECK-NEXT: sbcs.w r4, r6, r5
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; CHECK-NEXT: vmov q0[2], q0[0], r12, r2
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; CHECK-NEXT: cset r4, lt
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; CHECK-NEXT: cmp.w r3, r1, lsr #31
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; CHECK-NEXT: it ne
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; CHECK-NEXT: eorne r4, r4, #1
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; CHECK-NEXT: bfi r3, lr, #0, #8
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; CHECK-NEXT: rsbs r1, r4, #0
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; CHECK-NEXT: vmov q0[3], q0[1], r0, r6
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; CHECK-NEXT: bfi r3, r1, #8, #8
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; CHECK-NEXT: asrs r1, r6, #31
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; CHECK-NEXT: asrs r0, r0, #31
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; CHECK-NEXT: vmsr p0, r3
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; CHECK-NEXT: vmov q1[2], q1[0], r0, r1
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; CHECK-NEXT: vmov q1[3], q1[1], r0, r1
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; CHECK-NEXT: adr r0, .LCPI3_0
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; CHECK-NEXT: vldrw.u32 q2, [r0]
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; CHECK-NEXT: veor q1, q1, q2
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: pop {r4, r5, r6, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI3_0:
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 2147483648 @ 0x80000000
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 2147483648 @ 0x80000000
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entry:
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%0 = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @uadd_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
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; CHECK-LABEL: uadd_int8_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqadd.u8 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @uadd_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: uadd_int16_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqadd.u16 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @uadd_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LABEL: uadd_int32_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqadd.u32 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @uadd_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
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; CHECK-LABEL: uadd_int64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r7, lr}
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; CHECK-NEXT: push {r4, r5, r7, lr}
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; CHECK-NEXT: vmov r0, r1, d3
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; CHECK-NEXT: vmov r2, r3, d1
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; CHECK-NEXT: adds r5, r2, r0
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; CHECK-NEXT: adc.w lr, r3, r1
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; CHECK-NEXT: subs r2, r5, r2
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; CHECK-NEXT: sbcs.w r2, lr, r3
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; CHECK-NEXT: vmov r3, r12, d2
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; CHECK-NEXT: vmov r1, r4, d0
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; CHECK-NEXT: csetm r2, lo
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; CHECK-NEXT: adds r3, r3, r1
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; CHECK-NEXT: adc.w r0, r4, r12
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; CHECK-NEXT: subs r1, r3, r1
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; CHECK-NEXT: sbcs.w r1, r0, r4
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; CHECK-NEXT: vmov q1[2], q1[0], r3, r5
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; CHECK-NEXT: csetm r1, lo
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; CHECK-NEXT: vmov q1[3], q1[1], r0, lr
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; CHECK-NEXT: vmov q0[2], q0[0], r1, r2
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; CHECK-NEXT: vmov q0[3], q0[1], r1, r2
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; CHECK-NEXT: vorr q0, q1, q0
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; CHECK-NEXT: pop {r4, r5, r7, pc}
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entry:
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%0 = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @ssub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
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; CHECK-LABEL: ssub_int8_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqsub.s8 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @ssub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: ssub_int16_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqsub.s16 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @ssub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LABEL: ssub_int32_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqsub.s32 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @ssub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
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; CHECK-LABEL: ssub_int64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r7, lr}
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; CHECK-NEXT: push {r4, r5, r7, lr}
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; CHECK-NEXT: vmov r0, r1, d3
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; CHECK-NEXT: vmov r2, r3, d1
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; CHECK-NEXT: subs.w r12, r2, r0
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; CHECK-NEXT: vmov r2, r4, d0
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; CHECK-NEXT: sbcs.w r0, r3, r1
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; CHECK-NEXT: mrs r1, apsr
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; CHECK-NEXT: cmp.w r0, #-1
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; CHECK-NEXT: cset r3, gt
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; CHECK-NEXT: msr apsr_nzcvq, r1
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; CHECK-NEXT: vmov r1, lr, d2
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; CHECK-NEXT: it ge
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; CHECK-NEXT: lsrge r3, r0, #31
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; CHECK-NEXT: subs r5, r2, r1
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; CHECK-NEXT: sbcs.w r2, r4, lr
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; CHECK-NEXT: mrs r4, apsr
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; CHECK-NEXT: cmp.w r2, #-1
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; CHECK-NEXT: vmov q0[2], q0[0], r5, r12
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; CHECK-NEXT: cset r1, gt
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; CHECK-NEXT: msr apsr_nzcvq, r4
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; CHECK-NEXT: it ge
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; CHECK-NEXT: lsrge r1, r2, #31
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; CHECK-NEXT: movs r4, #0
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: vmov q0[3], q0[1], r2, r0
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; CHECK-NEXT: bfi r4, r1, #0, #8
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; CHECK-NEXT: rsbs r1, r3, #0
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; CHECK-NEXT: bfi r4, r1, #8, #8
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; CHECK-NEXT: asrs r0, r0, #31
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; CHECK-NEXT: asrs r1, r2, #31
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; CHECK-NEXT: vmsr p0, r4
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; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
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; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
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; CHECK-NEXT: adr r0, .LCPI11_0
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; CHECK-NEXT: vldrw.u32 q2, [r0]
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; CHECK-NEXT: veor q1, q1, q2
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; CHECK-NEXT: vpsel q0, q1, q0
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; CHECK-NEXT: pop {r4, r5, r7, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI11_0:
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 2147483648 @ 0x80000000
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 2147483648 @ 0x80000000
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entry:
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%0 = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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ret <2 x i64> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
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; CHECK-LABEL: usub_int8_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqsub.u8 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @usub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
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; CHECK-LABEL: usub_int16_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqsub.u16 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @usub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LABEL: usub_int32_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vqsub.u32 q0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @usub_int64_t(<2 x i64> %src1, <2 x i64> %src2) {
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; CHECK-LABEL: usub_int64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r7, lr}
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; CHECK-NEXT: push {r4, r5, r7, lr}
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; CHECK-NEXT: vmov r0, r1, d3
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; CHECK-NEXT: vmov r2, r3, d1
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; CHECK-NEXT: subs r5, r2, r0
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; CHECK-NEXT: sbc.w lr, r3, r1
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; CHECK-NEXT: subs r2, r2, r5
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; CHECK-NEXT: sbcs.w r2, r3, lr
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; CHECK-NEXT: vmov r3, r12, d2
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; CHECK-NEXT: vmov r1, r4, d0
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; CHECK-NEXT: csetm r2, lo
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; CHECK-NEXT: subs r3, r1, r3
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; CHECK-NEXT: sbc.w r0, r4, r12
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; CHECK-NEXT: subs r1, r1, r3
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; CHECK-NEXT: sbcs.w r1, r4, r0
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; CHECK-NEXT: vmov q1[2], q1[0], r3, r5
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; CHECK-NEXT: csetm r1, lo
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; CHECK-NEXT: vmov q1[3], q1[1], r0, lr
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; CHECK-NEXT: vmov q0[2], q0[0], r1, r2
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; CHECK-NEXT: vmov q0[3], q0[1], r1, r2
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; CHECK-NEXT: vbic q0, q1, q0
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; CHECK-NEXT: pop {r4, r5, r7, pc}
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entry:
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%0 = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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ret <2 x i64> %0
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}
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declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
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declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
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declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
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declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
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declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
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declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
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declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
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declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
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declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
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declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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declare <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
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declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
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declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
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declare <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %src1, <2 x i64> %src2)
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