derek.holloway
7502bf64a4
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1016 lines
37 KiB
LLVM
1016 lines
37 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LV,CHECKFP16
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-LV,CHECKFP
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; f16
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define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) {
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; CHECK-LABEL: shuffle1_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrev64.16 q1, q0
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; CHECK-NEXT: vmov.f32 s0, s6
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; CHECK-NEXT: vmov.f32 s1, s7
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; CHECK-NEXT: vmov.f32 s2, s4
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; CHECK-NEXT: vmov.f32 s3, s5
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @shuffle2_f16(<8 x half> %src) {
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; CHECK-LABEL: shuffle2_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @shuffle3_f16(<8 x half> %src) {
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; CHECKFP16-LABEL: shuffle3_f16:
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; CHECKFP16: @ %bb.0: @ %entry
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; CHECKFP16-NEXT: vmov q1, q0
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; CHECKFP16-NEXT: vmov.u16 r0, q0[7]
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; CHECKFP16-NEXT: vmov.16 q0[2], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q1[6]
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; CHECKFP16-NEXT: vmov.16 q0[3], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q1[3]
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; CHECKFP16-NEXT: vmov.16 q0[4], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q1[1]
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; CHECKFP16-NEXT: vmov.16 q0[5], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q1[2]
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; CHECKFP16-NEXT: vmov.16 q0[6], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q1[0]
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; CHECKFP16-NEXT: vmov.16 q0[7], r0
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; CHECKFP16-NEXT: vmov.f32 s0, s6
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; CHECKFP16-NEXT: bx lr
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;
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; CHECKFP-LABEL: shuffle3_f16:
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; CHECKFP: @ %bb.0: @ %entry
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; CHECKFP-NEXT: vmovx.f16 s5, s3
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; CHECKFP-NEXT: vmovx.f16 s6, s1
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; CHECKFP-NEXT: vmovx.f16 s4, s0
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; CHECKFP-NEXT: vins.f16 s1, s0
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; CHECKFP-NEXT: vins.f16 s6, s4
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; CHECKFP-NEXT: vins.f16 s5, s3
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; CHECKFP-NEXT: vmov.f32 s4, s2
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; CHECKFP-NEXT: vmov.f32 s7, s1
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; CHECKFP-NEXT: vmov q0, q1
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; CHECKFP-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 4, i32 5, i32 7, i32 6, i32 3, i32 1, i32 2, i32 0>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @shuffle5_f16(<8 x half> %src) {
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; CHECK-LABEL: shuffle5_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrev64.16 q1, q0
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; CHECK-NEXT: vmov q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @shuffle6_f16(<8 x half> %src) {
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; CHECK-LABEL: shuffle6_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vrev32.16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @oneoff11_f16(<8 x half> %src1, <8 x half> %src2) {
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; CHECKFP16-LABEL: oneoff11_f16:
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; CHECKFP16: @ %bb.0: @ %entry
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; CHECKFP16-NEXT: vmov.u16 r0, q0[1]
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; CHECKFP16-NEXT: vmov.16 q1[2], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q0[3]
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; CHECKFP16-NEXT: vmov.16 q1[3], r0
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; CHECKFP16-NEXT: vmov.f32 s1, s5
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; CHECKFP16-NEXT: bx lr
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;
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; CHECKFP-LABEL: oneoff11_f16:
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; CHECKFP: @ %bb.0: @ %entry
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; CHECKFP-NEXT: vmovx.f16 s4, s0
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; CHECKFP-NEXT: vmov r0, s4
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; CHECKFP-NEXT: vmov.16 q0[2], r0
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; CHECKFP-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 0, i32 1, i32 1, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @oneoff12_f16(<8 x half> %src1, <8 x half> %src2) {
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; CHECKFP16-LABEL: oneoff12_f16:
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; CHECKFP16: @ %bb.0: @ %entry
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; CHECKFP16-NEXT: vmov q2, q0
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; CHECKFP16-NEXT: vmovnb.i32 q2, q1
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; CHECKFP16-NEXT: vmov.f32 s9, s1
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; CHECKFP16-NEXT: vmov.f32 s10, s2
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; CHECKFP16-NEXT: vmov.f32 s11, s3
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; CHECKFP16-NEXT: vmov q0, q2
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; CHECKFP16-NEXT: bx lr
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;
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; CHECKFP-LABEL: oneoff12_f16:
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; CHECKFP: @ %bb.0: @ %entry
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; CHECKFP-NEXT: vmov r0, s4
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; CHECKFP-NEXT: vmov.16 q0[0], r0
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; CHECKFP-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @oneoff21_f16(<8 x half> %src1, <8 x half> %src2) {
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; CHECKFP16-LABEL: oneoff21_f16:
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; CHECKFP16: @ %bb.0: @ %entry
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; CHECKFP16-NEXT: vmov.u16 r0, q1[2]
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; CHECKFP16-NEXT: vmov.16 q2[2], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q0[0]
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; CHECKFP16-NEXT: vmov.16 q2[3], r0
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; CHECKFP16-NEXT: vmov.f32 s5, s9
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; CHECKFP16-NEXT: vmov q0, q1
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; CHECKFP16-NEXT: bx lr
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;
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; CHECKFP-LABEL: oneoff21_f16:
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; CHECKFP: @ %bb.0: @ %entry
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; CHECKFP-NEXT: vins.f16 s5, s0
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; CHECKFP-NEXT: vmov q0, q1
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; CHECKFP-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 8, i32 9, i32 10, i32 0, i32 12, i32 13, i32 14, i32 15>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @oneoff22_f16(<8 x half> %src1, <8 x half> %src2) {
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; CHECKFP16-LABEL: oneoff22_f16:
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; CHECKFP16: @ %bb.0: @ %entry
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; CHECKFP16-NEXT: vmov.u16 r0, q1[6]
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; CHECKFP16-NEXT: vmov.16 q0[0], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q1[1]
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; CHECKFP16-NEXT: vmov.16 q0[1], r0
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; CHECKFP16-NEXT: vmov.f32 s1, s5
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; CHECKFP16-NEXT: vmov.f32 s2, s6
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; CHECKFP16-NEXT: vmov.f32 s3, s7
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; CHECKFP16-NEXT: bx lr
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;
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; CHECKFP-LABEL: oneoff22_f16:
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; CHECKFP: @ %bb.0: @ %entry
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; CHECKFP-NEXT: vmov q0, q1
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; CHECKFP-NEXT: vmov r0, s3
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; CHECKFP-NEXT: vmov.16 q0[0], r0
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; CHECKFP-NEXT: bx lr
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entry:
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%out = shufflevector <8 x half> %src1, <8 x half> %src2, <8 x i32> <i32 14, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x half> %out
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}
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define arm_aapcs_vfpcc <8 x half> @shuffle2step_f16(<16 x half> %src) {
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; CHECKFP16-LABEL: shuffle2step_f16:
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; CHECKFP16: @ %bb.0: @ %entry
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; CHECKFP16-NEXT: .save {r4, r5, r6, lr}
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; CHECKFP16-NEXT: push {r4, r5, r6, lr}
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; CHECKFP16-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECKFP16-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECKFP16-NEXT: .pad #32
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; CHECKFP16-NEXT: sub sp, #32
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; CHECKFP16-NEXT: vmov q4, q1
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; CHECKFP16-NEXT: vshr.u32 q1, q1, #16
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; CHECKFP16-NEXT: add r6, sp, #16
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; CHECKFP16-NEXT: vmov.u16 r0, q0[0]
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; CHECKFP16-NEXT: vstrh.32 q1, [r6, #8]
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; CHECKFP16-NEXT: vshr.u32 q1, q0, #16
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; CHECKFP16-NEXT: mov r5, sp
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; CHECKFP16-NEXT: vstrh.32 q1, [r6]
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; CHECKFP16-NEXT: vstrh.32 q4, [r5, #8]
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; CHECKFP16-NEXT: vstrh.32 q0, [r5]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: vldrw.u32 q7, [r6]
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; CHECKFP16-NEXT: mov r4, r0
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; CHECKFP16-NEXT: vmov.u16 r0, q7[0]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r1, r0
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; CHECKFP16-NEXT: mov r0, r4
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; CHECKFP16-NEXT: bl __aeabi_fadd
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; CHECKFP16-NEXT: bl __aeabi_f2h
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; CHECKFP16-NEXT: vldrw.u32 q6, [r5]
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; CHECKFP16-NEXT: vmov.16 q5[0], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q6[1]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r4, r0
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; CHECKFP16-NEXT: vmov.u16 r0, q7[1]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r1, r0
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; CHECKFP16-NEXT: mov r0, r4
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; CHECKFP16-NEXT: bl __aeabi_fadd
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; CHECKFP16-NEXT: bl __aeabi_f2h
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; CHECKFP16-NEXT: vmov.16 q5[1], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q6[2]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r4, r0
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; CHECKFP16-NEXT: vmov.u16 r0, q7[2]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r1, r0
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; CHECKFP16-NEXT: mov r0, r4
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; CHECKFP16-NEXT: bl __aeabi_fadd
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; CHECKFP16-NEXT: bl __aeabi_f2h
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; CHECKFP16-NEXT: vmov.16 q5[2], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q6[3]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r4, r0
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; CHECKFP16-NEXT: vmov.u16 r0, q7[3]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r1, r0
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; CHECKFP16-NEXT: mov r0, r4
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; CHECKFP16-NEXT: bl __aeabi_fadd
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; CHECKFP16-NEXT: bl __aeabi_f2h
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; CHECKFP16-NEXT: vmov.16 q5[3], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q6[4]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r4, r0
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; CHECKFP16-NEXT: vmov.u16 r0, q7[4]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r1, r0
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; CHECKFP16-NEXT: mov r0, r4
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; CHECKFP16-NEXT: bl __aeabi_fadd
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; CHECKFP16-NEXT: bl __aeabi_f2h
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; CHECKFP16-NEXT: vmov.16 q5[4], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q6[5]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r4, r0
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; CHECKFP16-NEXT: vmov.u16 r0, q7[5]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r1, r0
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; CHECKFP16-NEXT: mov r0, r4
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; CHECKFP16-NEXT: bl __aeabi_fadd
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; CHECKFP16-NEXT: bl __aeabi_f2h
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; CHECKFP16-NEXT: vmov.16 q5[5], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q6[6]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r4, r0
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; CHECKFP16-NEXT: vmov.u16 r0, q7[6]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r1, r0
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; CHECKFP16-NEXT: mov r0, r4
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; CHECKFP16-NEXT: bl __aeabi_fadd
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; CHECKFP16-NEXT: bl __aeabi_f2h
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; CHECKFP16-NEXT: vmov.16 q5[6], r0
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; CHECKFP16-NEXT: vmov.u16 r0, q4[7]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r4, r0
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; CHECKFP16-NEXT: vmov.u16 r0, q6[7]
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; CHECKFP16-NEXT: bl __aeabi_h2f
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; CHECKFP16-NEXT: mov r1, r4
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; CHECKFP16-NEXT: bl __aeabi_fadd
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; CHECKFP16-NEXT: bl __aeabi_f2h
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; CHECKFP16-NEXT: vmov.16 q5[7], r0
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; CHECKFP16-NEXT: vmov q0, q5
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; CHECKFP16-NEXT: add sp, #32
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; CHECKFP16-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
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; CHECKFP16-NEXT: pop {r4, r5, r6, pc}
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;
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; CHECKFP-LABEL: shuffle2step_f16:
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; CHECKFP: @ %bb.0: @ %entry
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; CHECKFP-NEXT: vmovx.f16 s8, s0
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; CHECKFP-NEXT: vmovx.f16 s10, s1
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; CHECKFP-NEXT: vins.f16 s8, s10
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; CHECKFP-NEXT: vmovx.f16 s9, s2
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; CHECKFP-NEXT: vmovx.f16 s10, s3
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; CHECKFP-NEXT: vmovx.f16 s12, s5
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; CHECKFP-NEXT: vins.f16 s9, s10
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; CHECKFP-NEXT: vmovx.f16 s10, s4
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; CHECKFP-NEXT: vins.f16 s10, s12
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; CHECKFP-NEXT: vmovx.f16 s11, s6
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; CHECKFP-NEXT: vmovx.f16 s12, s7
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; CHECKFP-NEXT: vins.f16 s2, s3
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; CHECKFP-NEXT: vins.f16 s6, s7
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; CHECKFP-NEXT: vins.f16 s4, s5
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; CHECKFP-NEXT: vins.f16 s0, s1
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; CHECKFP-NEXT: vmov.f32 s1, s2
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; CHECKFP-NEXT: vins.f16 s11, s12
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; CHECKFP-NEXT: vmov.f32 s2, s4
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; CHECKFP-NEXT: vmov.f32 s3, s6
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; CHECKFP-NEXT: vadd.f16 q0, q0, q2
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; CHECKFP-NEXT: bx lr
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entry:
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%s1 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%s2 = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
|
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%r = fadd <8 x half> %s1, %s2
|
|
ret <8 x half> %r
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
|
|
; CHECKFP16-LABEL: shuffle3step_f16:
|
|
; CHECKFP16: @ %bb.0: @ %entry
|
|
; CHECKFP16-NEXT: .save {r4, r5, r6, r7, r8, lr}
|
|
; CHECKFP16-NEXT: push.w {r4, r5, r6, r7, r8, lr}
|
|
; CHECKFP16-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
|
|
; CHECKFP16-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
|
|
; CHECKFP16-NEXT: .pad #64
|
|
; CHECKFP16-NEXT: sub sp, #64
|
|
; CHECKFP16-NEXT: vmov q6, q0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q2[2]
|
|
; CHECKFP16-NEXT: vmov.16 q0[6], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q2[5]
|
|
; CHECKFP16-NEXT: vmov.u16 r7, q6[0]
|
|
; CHECKFP16-NEXT: vmov.16 q0[7], r0
|
|
; CHECKFP16-NEXT: vmov.16 q7[0], r7
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[3]
|
|
; CHECKFP16-NEXT: vmov.16 q7[1], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[6]
|
|
; CHECKFP16-NEXT: vmov.16 q7[2], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q1[1]
|
|
; CHECKFP16-NEXT: vmov.16 q7[3], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r8, q1[4]
|
|
; CHECKFP16-NEXT: vmov.16 q7[4], r8
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q1[7]
|
|
; CHECKFP16-NEXT: vmov.16 q7[5], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[2]
|
|
; CHECKFP16-NEXT: vmov.f32 s0, s28
|
|
; CHECKFP16-NEXT: vmov.u16 r6, q1[3]
|
|
; CHECKFP16-NEXT: vmov.f32 s1, s29
|
|
; CHECKFP16-NEXT: vmov q5, q1
|
|
; CHECKFP16-NEXT: vmov.f32 s2, s30
|
|
; CHECKFP16-NEXT: vstrw.32 q2, [sp, #48] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: vstrw.32 q0, [sp, #32] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: vmov.u16 r5, q0[6]
|
|
; CHECKFP16-NEXT: vmov.16 q0[0], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[5]
|
|
; CHECKFP16-NEXT: vmov.16 q0[1], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q1[0]
|
|
; CHECKFP16-NEXT: vmov.16 q0[2], r0
|
|
; CHECKFP16-NEXT: vmov.16 q0[3], r6
|
|
; CHECKFP16-NEXT: vmov.f32 s2, s23
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[0]
|
|
; CHECKFP16-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[1]
|
|
; CHECKFP16-NEXT: vmov.16 q4[0], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[4]
|
|
; CHECKFP16-NEXT: vmov.16 q4[1], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[7]
|
|
; CHECKFP16-NEXT: vmov.16 q4[2], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[2]
|
|
; CHECKFP16-NEXT: vmov.16 q4[3], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[5]
|
|
; CHECKFP16-NEXT: vmov.16 q4[4], r0
|
|
; CHECKFP16-NEXT: mov r0, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[0]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[0]
|
|
; CHECKFP16-NEXT: vmov.16 q1[5], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[3]
|
|
; CHECKFP16-NEXT: vmov.16 q1[6], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[6]
|
|
; CHECKFP16-NEXT: vmov.16 q1[7], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q1[6]
|
|
; CHECKFP16-NEXT: vstrw.32 q1, [sp, #16] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vldrw.u32 q6, [sp] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.16 q5[0], r4
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[1]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[1]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[1]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vmov.16 q5[1], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[2]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[2]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[2]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vmov.16 q5[2], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[3]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[3]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vmov.16 q5[3], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[4]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: mov r0, r8
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[4]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vldrw.u32 q0, [sp, #48] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: vmov.16 q5[4], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[4]
|
|
; CHECKFP16-NEXT: vmov.u16 r4, q0[7]
|
|
; CHECKFP16-NEXT: vmov.16 q4[6], r0
|
|
; CHECKFP16-NEXT: vmov.16 q4[7], r4
|
|
; CHECKFP16-NEXT: vmov.f32 s18, s0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[5]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: vldrw.u32 q6, [sp, #16] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[5]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[5]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vmov.16 q5[5], r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[6]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: vmov.16 q5[6], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[7]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[7]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vmov.16 q5[7], r0
|
|
; CHECKFP16-NEXT: vmov q0, q5
|
|
; CHECKFP16-NEXT: add sp, #64
|
|
; CHECKFP16-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
|
|
; CHECKFP16-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
|
|
;
|
|
; CHECKFP-LABEL: shuffle3step_f16:
|
|
; CHECKFP: @ %bb.0: @ %entry
|
|
; CHECKFP-NEXT: .vsave {d8, d9}
|
|
; CHECKFP-NEXT: vpush {d8, d9}
|
|
; CHECKFP-NEXT: vmov.f32 s13, s4
|
|
; CHECKFP-NEXT: vmovx.f16 s4, s4
|
|
; CHECKFP-NEXT: vmovx.f16 s17, s3
|
|
; CHECKFP-NEXT: vins.f16 s3, s4
|
|
; CHECKFP-NEXT: vmovx.f16 s4, s7
|
|
; CHECKFP-NEXT: vmovx.f16 s18, s6
|
|
; CHECKFP-NEXT: vmovx.f16 s16, s0
|
|
; CHECKFP-NEXT: vins.f16 s6, s4
|
|
; CHECKFP-NEXT: vmovx.f16 s14, s2
|
|
; CHECKFP-NEXT: vmov.f32 s12, s1
|
|
; CHECKFP-NEXT: vmovx.f16 s4, s10
|
|
; CHECKFP-NEXT: vmovx.f16 s19, s9
|
|
; CHECKFP-NEXT: vins.f16 s12, s14
|
|
; CHECKFP-NEXT: vmovx.f16 s14, s5
|
|
; CHECKFP-NEXT: vins.f16 s16, s2
|
|
; CHECKFP-NEXT: vmovx.f16 s2, s11
|
|
; CHECKFP-NEXT: vmovx.f16 s15, s8
|
|
; CHECKFP-NEXT: vins.f16 s18, s8
|
|
; CHECKFP-NEXT: vmovx.f16 s8, s1
|
|
; CHECKFP-NEXT: vins.f16 s9, s4
|
|
; CHECKFP-NEXT: vins.f16 s13, s14
|
|
; CHECKFP-NEXT: vmov.f32 s14, s7
|
|
; CHECKFP-NEXT: vins.f16 s10, s2
|
|
; CHECKFP-NEXT: vmov.f32 s1, s3
|
|
; CHECKFP-NEXT: vins.f16 s19, s11
|
|
; CHECKFP-NEXT: vins.f16 s17, s5
|
|
; CHECKFP-NEXT: vins.f16 s0, s8
|
|
; CHECKFP-NEXT: vmov.f32 s2, s6
|
|
; CHECKFP-NEXT: vmov.f32 s3, s9
|
|
; CHECKFP-NEXT: vins.f16 s14, s15
|
|
; CHECKFP-NEXT: vmov.f32 s15, s10
|
|
; CHECKFP-NEXT: vadd.f16 q0, q0, q4
|
|
; CHECKFP-NEXT: vadd.f16 q0, q0, q3
|
|
; CHECKFP-NEXT: vpop {d8, d9}
|
|
; CHECKFP-NEXT: bx lr
|
|
entry:
|
|
%s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
|
|
%s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
|
|
%s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
|
|
%a = fadd <8 x half> %s1, %s2
|
|
%r = fadd <8 x half> %a, %s3
|
|
ret <8 x half> %r
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <8 x half> @shuffle4step_f16(<32 x half> %src) {
|
|
; CHECKFP16-LABEL: shuffle4step_f16:
|
|
; CHECKFP16: @ %bb.0: @ %entry
|
|
; CHECKFP16-NEXT: .save {r4, r5, r6, r7, lr}
|
|
; CHECKFP16-NEXT: push {r4, r5, r6, r7, lr}
|
|
; CHECKFP16-NEXT: .pad #4
|
|
; CHECKFP16-NEXT: sub sp, #4
|
|
; CHECKFP16-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
|
|
; CHECKFP16-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
|
|
; CHECKFP16-NEXT: .pad #80
|
|
; CHECKFP16-NEXT: sub sp, #80
|
|
; CHECKFP16-NEXT: vmov q7, q0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[1]
|
|
; CHECKFP16-NEXT: vmov.16 q0[0], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[5]
|
|
; CHECKFP16-NEXT: vmov.16 q0[1], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q1[1]
|
|
; CHECKFP16-NEXT: vmov.16 q0[2], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q1[5]
|
|
; CHECKFP16-NEXT: vmov.16 q0[3], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r5, q7[0]
|
|
; CHECKFP16-NEXT: vmov q5, q0
|
|
; CHECKFP16-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: vmov.16 q0[0], r5
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[4]
|
|
; CHECKFP16-NEXT: vmov.16 q0[1], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q1[0]
|
|
; CHECKFP16-NEXT: vmov.16 q0[2], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q1[4]
|
|
; CHECKFP16-NEXT: vmov.16 q0[3], r0
|
|
; CHECKFP16-NEXT: vstrw.32 q3, [sp, #48] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[1]
|
|
; CHECKFP16-NEXT: vstrw.32 q2, [sp, #32] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: vmov q4, q1
|
|
; CHECKFP16-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[1]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[3]
|
|
; CHECKFP16-NEXT: vmov.16 q6[0], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[7]
|
|
; CHECKFP16-NEXT: vmov.16 q6[1], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[3]
|
|
; CHECKFP16-NEXT: vmov.16 q6[2], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[7]
|
|
; CHECKFP16-NEXT: vmov.16 q6[3], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[2]
|
|
; CHECKFP16-NEXT: vmov.16 q5[0], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[6]
|
|
; CHECKFP16-NEXT: vmov.16 q5[1], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r4, q4[2]
|
|
; CHECKFP16-NEXT: vmov.16 q5[2], r4
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[6]
|
|
; CHECKFP16-NEXT: vmov.16 q5[3], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[1]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[1]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: mov r0, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: vldrw.u32 q7, [sp, #16] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[0]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[0]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[0]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vmov.16 q0[0], r0
|
|
; CHECKFP16-NEXT: vmov.16 q0[1], r6
|
|
; CHECKFP16-NEXT: vmov q4, q0
|
|
; CHECKFP16-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[2]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[2]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[2]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: vmov.16 q4[2], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[3]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[3]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[3]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[3]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vldrw.u32 q5, [sp, #32] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: vmov.16 q4[3], r0
|
|
; CHECKFP16-NEXT: vldrw.u32 q7, [sp, #48] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: vstrw.32 q4, [sp] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[1]
|
|
; CHECKFP16-NEXT: vmov.u16 r5, q5[5]
|
|
; CHECKFP16-NEXT: vmov.16 q0[4], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[1]
|
|
; CHECKFP16-NEXT: vmov.16 q0[5], r5
|
|
; CHECKFP16-NEXT: vmov.16 q0[6], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[5]
|
|
; CHECKFP16-NEXT: vmov.16 q0[7], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[0]
|
|
; CHECKFP16-NEXT: vmov q4, q0
|
|
; CHECKFP16-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: vmov.16 q0[4], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[4]
|
|
; CHECKFP16-NEXT: vmov.16 q0[5], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[0]
|
|
; CHECKFP16-NEXT: vmov.16 q0[6], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[4]
|
|
; CHECKFP16-NEXT: vmov.16 q0[7], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[4]
|
|
; CHECKFP16-NEXT: vstrw.32 q0, [sp, #64] @ 16-byte Spill
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[4]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[3]
|
|
; CHECKFP16-NEXT: vmov.16 q4[4], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[7]
|
|
; CHECKFP16-NEXT: vmov.16 q4[5], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[3]
|
|
; CHECKFP16-NEXT: vmov.16 q4[6], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[2]
|
|
; CHECKFP16-NEXT: vmov.16 q6[4], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q5[6]
|
|
; CHECKFP16-NEXT: vmov.16 q6[5], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[2]
|
|
; CHECKFP16-NEXT: vmov.16 q6[6], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[6]
|
|
; CHECKFP16-NEXT: vmov.16 q6[7], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r4, q7[7]
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[4]
|
|
; CHECKFP16-NEXT: vmov.16 q4[7], r4
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[4]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r7, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: mov r0, r7
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vldrw.u32 q5, [sp] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: vmov.16 q5[4], r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: vldrw.u32 q7, [sp, #64] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[5]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[5]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[5]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vmov.16 q5[5], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[6]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: vldrw.u32 q7, [sp, #16] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[6]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[6]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q4[6]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r6, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r6
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vldrw.u32 q0, [sp, #64] @ 16-byte Reload
|
|
; CHECKFP16-NEXT: vmov.16 q5[6], r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[7]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q7[7]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q6[7]
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: mov r4, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r5, r0
|
|
; CHECKFP16-NEXT: mov r0, r4
|
|
; CHECKFP16-NEXT: bl __aeabi_h2f
|
|
; CHECKFP16-NEXT: mov r1, r0
|
|
; CHECKFP16-NEXT: mov r0, r5
|
|
; CHECKFP16-NEXT: bl __aeabi_fadd
|
|
; CHECKFP16-NEXT: bl __aeabi_f2h
|
|
; CHECKFP16-NEXT: vmov q0, q5
|
|
; CHECKFP16-NEXT: vmov.16 q0[7], r0
|
|
; CHECKFP16-NEXT: add sp, #80
|
|
; CHECKFP16-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
|
|
; CHECKFP16-NEXT: add sp, #4
|
|
; CHECKFP16-NEXT: pop {r4, r5, r6, r7, pc}
|
|
;
|
|
; CHECKFP-LABEL: shuffle4step_f16:
|
|
; CHECKFP: @ %bb.0: @ %entry
|
|
; CHECKFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
|
|
; CHECKFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
|
|
; CHECKFP-NEXT: vmovx.f16 s18, s9
|
|
; CHECKFP-NEXT: vmovx.f16 s16, s11
|
|
; CHECKFP-NEXT: vins.f16 s18, s16
|
|
; CHECKFP-NEXT: vmovx.f16 s19, s13
|
|
; CHECKFP-NEXT: vmovx.f16 s16, s15
|
|
; CHECKFP-NEXT: vmovx.f16 s22, s8
|
|
; CHECKFP-NEXT: vins.f16 s19, s16
|
|
; CHECKFP-NEXT: vmovx.f16 s16, s1
|
|
; CHECKFP-NEXT: vmovx.f16 s20, s3
|
|
; CHECKFP-NEXT: vins.f16 s1, s3
|
|
; CHECKFP-NEXT: vmovx.f16 s3, s10
|
|
; CHECKFP-NEXT: vins.f16 s16, s20
|
|
; CHECKFP-NEXT: vmovx.f16 s17, s5
|
|
; CHECKFP-NEXT: vmovx.f16 s20, s7
|
|
; CHECKFP-NEXT: vins.f16 s22, s3
|
|
; CHECKFP-NEXT: vmovx.f16 s23, s12
|
|
; CHECKFP-NEXT: vmovx.f16 s3, s14
|
|
; CHECKFP-NEXT: vins.f16 s17, s20
|
|
; CHECKFP-NEXT: vins.f16 s23, s3
|
|
; CHECKFP-NEXT: vmovx.f16 s20, s0
|
|
; CHECKFP-NEXT: vmovx.f16 s3, s2
|
|
; CHECKFP-NEXT: vins.f16 s9, s11
|
|
; CHECKFP-NEXT: vins.f16 s13, s15
|
|
; CHECKFP-NEXT: vins.f16 s5, s7
|
|
; CHECKFP-NEXT: vins.f16 s20, s3
|
|
; CHECKFP-NEXT: vmovx.f16 s21, s4
|
|
; CHECKFP-NEXT: vmovx.f16 s3, s6
|
|
; CHECKFP-NEXT: vins.f16 s8, s10
|
|
; CHECKFP-NEXT: vins.f16 s12, s14
|
|
; CHECKFP-NEXT: vins.f16 s4, s6
|
|
; CHECKFP-NEXT: vins.f16 s21, s3
|
|
; CHECKFP-NEXT: vins.f16 s0, s2
|
|
; CHECKFP-NEXT: vmov.f32 s24, s1
|
|
; CHECKFP-NEXT: vmov.f32 s26, s9
|
|
; CHECKFP-NEXT: vmov.f32 s25, s5
|
|
; CHECKFP-NEXT: vmov.f32 s27, s13
|
|
; CHECKFP-NEXT: vmov.f32 s2, s8
|
|
; CHECKFP-NEXT: vadd.f16 q4, q6, q4
|
|
; CHECKFP-NEXT: vmov.f32 s1, s4
|
|
; CHECKFP-NEXT: vmov.f32 s3, s12
|
|
; CHECKFP-NEXT: vadd.f16 q0, q0, q5
|
|
; CHECKFP-NEXT: vadd.f16 q0, q0, q4
|
|
; CHECKFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
|
|
; CHECKFP-NEXT: bx lr
|
|
entry:
|
|
%s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
|
|
%s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
|
|
%s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
|
|
%s4 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
|
|
%a1 = fadd <8 x half> %s1, %s2
|
|
%a2 = fadd <8 x half> %s3, %s4
|
|
%r = fadd <8 x half> %a1, %a2
|
|
ret <8 x half> %r
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <8 x half> @insert_f16(half %a) {
|
|
; CHECKFP16-LABEL: insert_f16:
|
|
; CHECKFP16: @ %bb.0: @ %entry
|
|
; CHECKFP16-NEXT: vmov r0, s0
|
|
; CHECKFP16-NEXT: vmov.16 q0[0], r0
|
|
; CHECKFP16-NEXT: bx lr
|
|
;
|
|
; CHECKFP-LABEL: insert_f16:
|
|
; CHECKFP: @ %bb.0: @ %entry
|
|
; CHECKFP-NEXT: bx lr
|
|
entry:
|
|
%res = insertelement <8 x half> undef, half %a, i32 0
|
|
ret <8 x half> %res
|
|
}
|
|
|
|
define arm_aapcs_vfpcc half @extract_f16_0(<8 x half> %a) {
|
|
; CHECKFP16-LABEL: extract_f16_0:
|
|
; CHECKFP16: @ %bb.0: @ %entry
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[0]
|
|
; CHECKFP16-NEXT: vmov s0, r0
|
|
; CHECKFP16-NEXT: bx lr
|
|
;
|
|
; CHECKFP-LABEL: extract_f16_0:
|
|
; CHECKFP: @ %bb.0: @ %entry
|
|
; CHECKFP-NEXT: bx lr
|
|
entry:
|
|
%res = extractelement <8 x half> %a, i32 0
|
|
ret half %res
|
|
}
|
|
|
|
define arm_aapcs_vfpcc half @extract_f16_3(<8 x half> %a) {
|
|
; CHECKFP16-LABEL: extract_f16_3:
|
|
; CHECKFP16: @ %bb.0: @ %entry
|
|
; CHECKFP16-NEXT: vmov.u16 r0, q0[3]
|
|
; CHECKFP16-NEXT: vmov s0, r0
|
|
; CHECKFP16-NEXT: bx lr
|
|
;
|
|
; CHECKFP-LABEL: extract_f16_3:
|
|
; CHECKFP: @ %bb.0: @ %entry
|
|
; CHECKFP-NEXT: vmovx.f16 s0, s1
|
|
; CHECKFP-NEXT: bx lr
|
|
entry:
|
|
%res = extractelement <8 x half> %a, i32 3
|
|
ret half %res
|
|
}
|
|
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
|
; CHECK-LV: {{.*}}
|