derek.holloway
7502bf64a4
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40 lines
1.4 KiB
LLVM
40 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CHECK
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; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 -arm-data-bank-mask=-1 | FileCheck %s --check-prefix=NOBANK
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; This tests the cortex-m7 bank conflict hazard recognizer.
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; Normally both loads would be scheduled early (both in the first cycle) due to
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; their latency. But will bank conflict to TCM so are scheduled in different
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; cycles.
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define i32 @test(ptr %x0, i32 %y, i32 %z) {
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; CHECK-LABEL: test:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldr r3, [r0]
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; CHECK-NEXT: subs r1, r3, r1
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; CHECK-NEXT: ldr r0, [r0, #8]
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; CHECK-NEXT: subs r1, r1, r2
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; CHECK-NEXT: adds r1, #1
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; CHECK-NEXT: muls r0, r1, r0
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; CHECK-NEXT: bx lr
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;
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; NOBANK-LABEL: test:
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; NOBANK: @ %bb.0: @ %entry
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; NOBANK-NEXT: ldr r3, [r0]
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; NOBANK-NEXT: ldr r0, [r0, #8]
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; NOBANK-NEXT: subs r1, r3, r1
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; NOBANK-NEXT: subs r1, r1, r2
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; NOBANK-NEXT: adds r1, #1
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; NOBANK-NEXT: muls r0, r1, r0
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; NOBANK-NEXT: bx lr
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entry:
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%0 = load i32, ptr %x0, align 4
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%mul3 = add nsw i32 %0, 1
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%mul = sub nsw i32 %mul3, %y
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%sub = sub nsw i32 %mul, %z
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%arrayidx1 = getelementptr inbounds i32, ptr %x0, i32 2
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%1 = load i32, ptr %arrayidx1, align 4
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%mul2 = mul nsw i32 %sub, %1
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ret i32 %mul2
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}
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