derek.holloway
7502bf64a4
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415 lines
12 KiB
LLVM
415 lines
12 KiB
LLVM
; RUN: llc < %s -mtriple=ve | FileCheck %s
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;;; Test ‘shl’ instruction
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;;;
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;;; Syntax:
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;;; <result> = shl <ty> <op1>, <op2> ; yields ty:result
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;;; <result> = shl nuw <ty> <op1>, <op2> ; yields ty:result
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;;; <result> = shl nsw <ty> <op1>, <op2> ; yields ty:result
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;;; <result> = shl nuw nsw <ty> <op1>, <op2> ; yields ty:result
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;;;
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;;; Overview:
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;;; The ‘shl’ instruction returns the first operand shifted to the left
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;;; a specified number of bits.
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;;;
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;;; Arguments:
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;;; Both arguments to the ‘shl’ instruction must be the same integer or
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;;; vector of integer type. ‘op2’ is treated as an unsigned value.
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;;;
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;;; Semantics:
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;;; The value produced is op1 * 2op2 mod 2n, where n is the width of the
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;;; result. If op2 is (statically or dynamically) equal to or larger than
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;;; the number of bits in op1, this instruction returns a poison value.
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;;; If the arguments are vectors, each vector element of op1 is shifted by
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;;; the corresponding shift amount in op2.
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;;;
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;;; If the nuw keyword is present, then the shift produces a poison value
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;;; if it shifts out any non-zero bits. If the nsw keyword is present,
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;;; then the shift produces a poison value if it shifts out any bits that
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;;; disagree with the resultant sign bit.
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;;;
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;;; Example:
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;;; <result> = shl i32 4, %var ; yields i32: 4 << %var
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;;; <result> = shl i32 4, 2 ; yields i32: 16
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;;; <result> = shl i32 1, 10 ; yields i32: 1024
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;;; <result> = shl i32 1, 32 ; undefined
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;;; <result> = shl <2 x i32> < i32 1, i32 1>, < i32 1, i32 2>
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;;; ; yields: result=<2 x i32> < i32 2, i32 4>
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;;;
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;;; Note:
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;;; We test only i8/i16/i32/i64/i128 and unsigned of them.
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; Function Attrs: norecurse nounwind readnone
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define signext i8 @shl_i8_var(i8 signext %0, i8 signext %1) {
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; CHECK-LABEL: shl_i8_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (56)0
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: sll %s0, %s0, 56
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; CHECK-NEXT: sra.l %s0, %s0, 56
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = sext i8 %0 to i32
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%4 = zext i8 %1 to i32
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%5 = shl i32 %3, %4
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%6 = trunc i32 %5 to i8
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ret i8 %6
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i8 @shl_u8_var(i8 zeroext %0, i8 zeroext %1) {
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; CHECK-LABEL: shl_u8_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (56)0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = zext i8 %0 to i32
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%4 = zext i8 %1 to i32
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%5 = shl i32 %3, %4
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%6 = trunc i32 %5 to i8
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ret i8 %6
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i16 @shl_i16_var(i16 signext %0, i16 signext %1) {
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; CHECK-LABEL: shl_i16_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s1, %s1, (48)0
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: sll %s0, %s0, 48
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; CHECK-NEXT: sra.l %s0, %s0, 48
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = sext i16 %0 to i32
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%4 = zext i16 %1 to i32
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%5 = shl i32 %3, %4
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%6 = trunc i32 %5 to i16
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ret i16 %6
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i16 @shl_u16_var(i16 zeroext %0, i16 zeroext %1) {
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; CHECK-LABEL: shl_u16_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: and %s0, %s0, (48)0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = zext i16 %0 to i32
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%4 = zext i16 %1 to i32
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%5 = shl i32 %3, %4
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%6 = trunc i32 %5 to i16
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ret i16 %6
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @shl_i32_var(i32 signext %0, i32 signext %1) {
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; CHECK-LABEL: shl_i32_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = shl i32 %0, %1
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ret i32 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @shl_u32_var(i32 zeroext %0, i32 zeroext %1) {
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; CHECK-LABEL: shl_u32_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, %s1
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = shl i32 %0, %1
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ret i32 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @shl_i64_var(i64 %0, i64 %1) {
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; CHECK-LABEL: shl_i64_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = shl i64 %0, %1
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ret i64 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @shl_u64_var(i64 %0, i64 %1) {
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; CHECK-LABEL: shl_u64_var:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = shl i64 %0, %1
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ret i64 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @shl_i128_var(i128 %0, i128 %1) {
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; CHECK-LABEL: shl_i128_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: lea %s3, __ashlti3@lo
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; CHECK-NEXT: and %s3, %s3, (32)0
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; CHECK-NEXT: lea.sl %s12, __ashlti3@hi(, %s3)
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = shl i128 %0, %1
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ret i128 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @shl_u128_var(i128 %0, i128 %1) {
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; CHECK-LABEL: shl_u128_var:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: and %s2, %s2, (32)0
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; CHECK-NEXT: lea %s3, __ashlti3@lo
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; CHECK-NEXT: and %s3, %s3, (32)0
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; CHECK-NEXT: lea.sl %s12, __ashlti3@hi(, %s3)
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = shl i128 %0, %1
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ret i128 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i8 @shl_const_i8(i8 signext %0) {
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; CHECK-LABEL: shl_const_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (56)0
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; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
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; CHECK-NEXT: sll %s0, %s0, 56
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; CHECK-NEXT: sra.l %s0, %s0, 56
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = zext i8 %0 to i32
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%3 = shl i32 -4, %2
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%4 = trunc i32 %3 to i8
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ret i8 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i8 @shl_const_u8(i8 zeroext %0) {
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; CHECK-LABEL: shl_const_u8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
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; CHECK-NEXT: lea %s1, 252
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; CHECK-NEXT: and %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = zext i8 %0 to i32
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%3 = shl i32 -4, %2
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%4 = trunc i32 %3 to i8
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ret i8 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i16 @shl_const_i16(i16 signext %0) {
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; CHECK-LABEL: shl_const_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: and %s0, %s0, (48)0
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; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
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; CHECK-NEXT: sll %s0, %s0, 48
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; CHECK-NEXT: sra.l %s0, %s0, 48
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = zext i16 %0 to i32
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%3 = shl i32 -4, %2
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%4 = trunc i32 %3 to i16
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ret i16 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i16 @shl_const_u16(i16 zeroext %0) {
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; CHECK-LABEL: shl_const_u16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
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; CHECK-NEXT: lea %s1, 65532
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; CHECK-NEXT: and %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = zext i16 %0 to i32
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%3 = shl i32 -4, %2
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%4 = trunc i32 %3 to i16
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ret i16 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @shl_const_i32(i32 signext %0) {
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; CHECK-LABEL: shl_const_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = shl i32 -4, %0
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ret i32 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i32 @shl_const_u32(i32 zeroext %0) {
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; CHECK-LABEL: shl_const_u32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, (62)1, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = shl i32 -4, %0
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ret i32 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @shl_const_i64(i64 %0) {
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; CHECK-LABEL: shl_const_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %s0, (62)1, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = shl i64 -4, %0
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ret i64 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i64 @shl_const_u64(i64 %0) {
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; CHECK-LABEL: shl_const_u64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sll %s0, (62)1, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = shl i64 -4, %0
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ret i64 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @shl_const_i128(i128 %0) {
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; CHECK-LABEL: shl_const_i128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: and %s2, %s0, (32)0
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; CHECK-NEXT: lea %s0, __ashlti3@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __ashlti3@hi(, %s0)
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; CHECK-NEXT: or %s0, -4, (0)1
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; CHECK-NEXT: or %s1, -1, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i128 -4, %0
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ret i128 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define i128 @shl_const_u128(i128 %0) {
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; CHECK-LABEL: shl_const_u128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: and %s2, %s0, (32)0
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; CHECK-NEXT: lea %s0, __ashlti3@lo
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; CHECK-NEXT: and %s0, %s0, (32)0
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; CHECK-NEXT: lea.sl %s12, __ashlti3@hi(, %s0)
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; CHECK-NEXT: or %s0, -4, (0)1
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; CHECK-NEXT: or %s1, -1, (0)1
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; CHECK-NEXT: bsic %s10, (, %s12)
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; CHECK-NEXT: or %s11, 0, %s9
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%2 = shl i128 -4, %0
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ret i128 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i8 @shl_i8_const(i8 signext %0) {
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; CHECK-LABEL: shl_i8_const:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, 3
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; CHECK-NEXT: sll %s0, %s0, 56
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; CHECK-NEXT: sra.l %s0, %s0, 56
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = shl i8 %0, 3
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ret i8 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i8 @shl_u8_const(i8 zeroext %0) {
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; CHECK-LABEL: shl_u8_const:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, 3
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; CHECK-NEXT: lea %s1, 248
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; CHECK-NEXT: and %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = shl i8 %0, 3
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ret i8 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i16 @shl_i16_const(i16 signext %0) {
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; CHECK-LABEL: shl_i16_const:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, 7
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; CHECK-NEXT: sll %s0, %s0, 48
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; CHECK-NEXT: sra.l %s0, %s0, 48
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = shl i16 %0, 7
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ret i16 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i16 @shl_u16_const(i16 zeroext %0) {
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; CHECK-LABEL: shl_u16_const:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, 7
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; CHECK-NEXT: lea %s1, 65408
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; CHECK-NEXT: and %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = shl i16 %0, 7
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ret i16 %2
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}
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @shl_i32_const(i32 signext %0) {
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; CHECK-LABEL: shl_i32_const:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sla.w.sx %s0, %s0, 15
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; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%2 = shl i32 %0, 15
|
||
ret i32 %2
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define zeroext i32 @shl_u32_const(i32 zeroext %0) {
|
||
; CHECK-LABEL: shl_u32_const:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: sla.w.sx %s0, %s0, 15
|
||
; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%2 = shl i32 %0, 15
|
||
ret i32 %2
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define i64 @shl_i64_const(i64 %0) {
|
||
; CHECK-LABEL: shl_i64_const:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: sll %s0, %s0, 63
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%2 = shl i64 %0, 63
|
||
ret i64 %2
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define i64 @shl_u64_const(i64 %0) {
|
||
; CHECK-LABEL: shl_u64_const:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: sll %s0, %s0, 63
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%2 = shl i64 %0, 63
|
||
ret i64 %2
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define i128 @shl_i128_const(i128 %0) {
|
||
; CHECK-LABEL: shl_i128_const:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: sll %s1, %s0, 63
|
||
; CHECK-NEXT: or %s0, 0, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%2 = shl i128 %0, 127
|
||
ret i128 %2
|
||
}
|
||
|
||
; Function Attrs: norecurse nounwind readnone
|
||
define i128 @shl_u128_const(i128 %0) {
|
||
; CHECK-LABEL: shl_u128_const:
|
||
; CHECK: # %bb.0:
|
||
; CHECK-NEXT: sll %s1, %s0, 63
|
||
; CHECK-NEXT: or %s0, 0, (0)1
|
||
; CHECK-NEXT: b.l.t (, %s10)
|
||
%2 = shl i128 %0, 127
|
||
ret i128 %2
|
||
}
|