derek.holloway
7502bf64a4
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133 lines
4.7 KiB
LLVM
133 lines
4.7 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test vector move intrinsic instructions
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;;;
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;;; Note:
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;;; We test VMVivl and VMVivl_v, and VMVivml_v instructions.
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; Function Attrs: nounwind
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define void @vmv_vsvl(ptr %0, i32 signext %1) {
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; CHECK-LABEL: vmv_vsvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: vmv %v0, %s1, %v0
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; CHECK-NEXT: vst %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %0, i32 256)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvl(i32 %1, <256 x double> %3, i32 256)
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tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %0, i32 256)
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ret void
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}
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; Function Attrs: nounwind readonly
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declare <256 x double> @llvm.ve.vl.vld.vssl(i64, ptr, i32)
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmv.vsvl(i32, <256 x double>, i32)
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; Function Attrs: nounwind writeonly
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declare void @llvm.ve.vl.vst.vssl(<256 x double>, i64, ptr, i32)
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; Function Attrs: nounwind
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define void @vmv_vsvl_imm(ptr %0) {
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; CHECK-LABEL: vmv_vsvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: vmv %v0, 31, %v0
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; CHECK-NEXT: vst %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %0, i32 256)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvl(i32 31, <256 x double> %2, i32 256)
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tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 8, ptr %0, i32 256)
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ret void
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}
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; Function Attrs: nounwind
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define void @vmv_vsvvl(ptr %0, i32 signext %1) {
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; CHECK-LABEL: vmv_vsvvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea %s3, 128
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; CHECK-NEXT: lvl %s3
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; CHECK-NEXT: vmv %v0, %s1, %v0
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vst %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %0, i32 256)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvvl(i32 %1, <256 x double> %3, <256 x double> %3, i32 128)
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tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %0, i32 256)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmv.vsvvl(i32, <256 x double>, <256 x double>, i32)
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; Function Attrs: nounwind
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define void @vmv_vsvvl_imm(ptr %0) {
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; CHECK-LABEL: vmv_vsvvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: lea %s2, 128
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vmv %v0, 31, %v0
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vst %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %0, i32 256)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvvl(i32 31, <256 x double> %2, <256 x double> %2, i32 128)
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tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 8, ptr %0, i32 256)
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ret void
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}
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; Function Attrs: nounwind
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define void @vmv_vsvmvl(ptr %0, i32 signext %1) {
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; CHECK-LABEL: vmv_vsvmvl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s2, 256
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: and %s1, %s1, (32)0
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; CHECK-NEXT: lea %s3, 128
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; CHECK-NEXT: lvl %s3
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; CHECK-NEXT: vmv %v0, %s1, %v0, %vm1
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vst %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %0, i32 256)
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%4 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvmvl(i32 %1, <256 x double> %3, <256 x i1> undef, <256 x double> %3, i32 128)
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tail call void @llvm.ve.vl.vst.vssl(<256 x double> %4, i64 8, ptr %0, i32 256)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <256 x double> @llvm.ve.vl.vmv.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32)
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; Function Attrs: nounwind
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define void @vmv_vsvmvl_imm(ptr %0) {
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; CHECK-LABEL: vmv_vsvmvl_imm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s1, 256
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vld %v0, 8, %s0
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; CHECK-NEXT: lea %s2, 128
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; CHECK-NEXT: lvl %s2
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; CHECK-NEXT: vmv %v0, 31, %v0, %vm1
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; CHECK-NEXT: lvl %s1
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; CHECK-NEXT: vst %v0, 8, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call fast <256 x double> @llvm.ve.vl.vld.vssl(i64 8, ptr %0, i32 256)
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%3 = tail call fast <256 x double> @llvm.ve.vl.vmv.vsvmvl(i32 31, <256 x double> %2, <256 x i1> undef, <256 x double> %2, i32 128)
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tail call void @llvm.ve.vl.vst.vssl(<256 x double> %3, i64 8, ptr %0, i32 256)
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ret void
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}
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