TheRock/compiler/amd-llvm/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512F
--- |
  define <16 x i32> @test_load_v16i32_noalign(ptr %p1) {
    %r = load <16 x i32>, ptr %p1, align 1
    ret <16 x i32> %r
  }

  define <16 x i32> @test_load_v16i32_align(ptr %p1) {
    %r = load <16 x i32>, ptr %p1, align 32
    ret <16 x i32> %r
  }

  define void @test_store_v16i32_noalign(<16 x i32> %val, ptr %p1) {
    store <16 x i32> %val, ptr %p1, align 1
    ret void
  }

  define void @test_store_v16i32_align(<16 x i32> %val, ptr %p1) {
    store <16 x i32> %val, ptr %p1, align 32
    ret void
  }

...
---
name:            test_load_v16i32_noalign
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $rdi

    ; AVX512F-LABEL: name: test_load_v16i32_noalign
    ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
    ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load (<16 x s32>) from %ir.p1, align 1)
    ; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]]
    ; AVX512F: RET 0, implicit $zmm0
    %0(p0) = COPY $rdi
    %1(<16 x s32>) = G_LOAD %0(p0) :: (load (<16 x s32>) from %ir.p1, align 1)
    $zmm0 = COPY %1(<16 x s32>)
    RET 0, implicit $zmm0

...
---
name:            test_load_v16i32_align
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $rdi

    ; AVX512F-LABEL: name: test_load_v16i32_align
    ; AVX512F: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
    ; AVX512F: [[VMOVUPSZrm:%[0-9]+]]:vr512 = VMOVUPSZrm [[COPY]], 1, $noreg, 0, $noreg :: (load (<16 x s32>) from %ir.p1, align 32)
    ; AVX512F: $zmm0 = COPY [[VMOVUPSZrm]]
    ; AVX512F: RET 0, implicit $zmm0
    %0(p0) = COPY $rdi
    %1(<16 x s32>) = G_LOAD %0(p0) :: (load (<16 x s32>) from %ir.p1, align 32)
    $zmm0 = COPY %1(<16 x s32>)
    RET 0, implicit $zmm0

...
---
name:            test_store_v16i32_noalign
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $rdi, $zmm0

    ; AVX512F-LABEL: name: test_store_v16i32_noalign
    ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
    ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
    ; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (<16 x s32>) into %ir.p1, align 1)
    ; AVX512F: RET 0
    %0(<16 x s32>) = COPY $zmm0
    %1(p0) = COPY $rdi
    G_STORE %0(<16 x s32>), %1(p0) :: (store (<16 x s32>) into %ir.p1, align 1)
    RET 0

...
---
name:            test_store_v16i32_align
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: gpr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $rdi, $zmm0

    ; AVX512F-LABEL: name: test_store_v16i32_align
    ; AVX512F: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
    ; AVX512F: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
    ; AVX512F: VMOVUPSZmr [[COPY1]], 1, $noreg, 0, $noreg, [[COPY]] :: (store (<16 x s32>) into %ir.p1, align 32)
    ; AVX512F: RET 0
    %0(<16 x s32>) = COPY $zmm0
    %1(p0) = COPY $rdi
    G_STORE %0(<16 x s32>), %1(p0) :: (store (<16 x s32>) into %ir.p1, align 32)
    RET 0

...