derek.holloway
7502bf64a4
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172 lines
6.5 KiB
LLVM
172 lines
6.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2 -mattr=+amx-avx512 -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2 -mattr=+amx-avx512 -verify-machineinstrs -enable-ipra | FileCheck -check-prefix=IPRA %s
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; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2 -mattr=+amx-avx512 -verify-machineinstrs | FileCheck -check-prefix=O0 %s
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@buf = dso_local global [3072 x i8] zeroinitializer, align 64
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define internal void @foo() {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: retq
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;
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; IPRA-LABEL: foo:
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; IPRA: # %bb.0: # %entry
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; IPRA-NEXT: retq
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;
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; O0-LABEL: foo:
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; O0: # %bb.0: # %entry
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; O0-NEXT: retq
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entry:
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ret void
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}
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define dso_local <16 x i32> @test_api(i16 signext %0, i16 signext %1) nounwind {
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; CHECK-LABEL: test_api:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushq %rbp
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; CHECK-NEXT: pushq %r14
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; CHECK-NEXT: pushq %rbx
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; CHECK-NEXT: subq $2112, %rsp # imm = 0x840
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; CHECK-NEXT: movl %esi, %ebx
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; CHECK-NEXT: movl %edi, %ebp
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; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: vmovups %zmm0, (%rsp)
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; CHECK-NEXT: movb $1, (%rsp)
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; CHECK-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw %bx, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb %bpl, {{[0-9]+}}(%rsp)
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; CHECK-NEXT: ldtilecfg (%rsp)
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; CHECK-NEXT: movl $buf, %eax
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; CHECK-NEXT: movl $32, %ecx
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; CHECK-NEXT: movw $8, %r14w
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; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm0
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tilestored %tmm0, 1088(%rsp,%rax) # 1024-byte Folded Spill
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; CHECK-NEXT: movl $buf+1024, %eax
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; CHECK-NEXT: tileloadd (%rax,%rcx), %tmm1
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tilestored %tmm1, 64(%rsp,%rax) # 1024-byte Folded Spill
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: callq foo
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; CHECK-NEXT: ldtilecfg (%rsp)
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; CHECK-NEXT: movabsq $64, %rax
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; CHECK-NEXT: tileloadd 64(%rsp,%rax), %tmm1 # 1024-byte Folded Reload
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; CHECK-NEXT: tilemovrow $2, %tmm1, %zmm0
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; CHECK-NEXT: tileloadd 1088(%rsp,%rax), %tmm0 # 1024-byte Folded Reload
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; CHECK-NEXT: tilemovrow $2, %tmm0, %zmm1
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; CHECK-NEXT: vpaddd %zmm1, %zmm0, %zmm0
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; CHECK-NEXT: addq $2112, %rsp # imm = 0x840
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; CHECK-NEXT: popq %rbx
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; CHECK-NEXT: popq %r14
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; CHECK-NEXT: popq %rbp
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; CHECK-NEXT: tilerelease
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; CHECK-NEXT: retq
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;
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; IPRA-LABEL: test_api:
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; IPRA: # %bb.0:
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; IPRA-NEXT: subq $72, %rsp
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; IPRA-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; IPRA-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp)
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; IPRA-NEXT: movb $1, {{[0-9]+}}(%rsp)
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; IPRA-NEXT: movw $8, {{[0-9]+}}(%rsp)
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; IPRA-NEXT: movb $8, {{[0-9]+}}(%rsp)
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; IPRA-NEXT: movw %si, {{[0-9]+}}(%rsp)
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; IPRA-NEXT: movb %dil, {{[0-9]+}}(%rsp)
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; IPRA-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; IPRA-NEXT: movl $buf, %eax
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; IPRA-NEXT: movl $32, %ecx
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; IPRA-NEXT: movw $8, %dx
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; IPRA-NEXT: tileloadd (%rax,%rcx), %tmm0
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; IPRA-NEXT: movl $buf+1024, %eax
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; IPRA-NEXT: tileloadd (%rax,%rcx), %tmm1
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; IPRA-NEXT: callq foo
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; IPRA-NEXT: tilemovrow $2, %tmm1, %zmm0
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; IPRA-NEXT: tilemovrow $2, %tmm0, %zmm1
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; IPRA-NEXT: vpaddd %zmm1, %zmm0, %zmm0
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; IPRA-NEXT: addq $72, %rsp
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; IPRA-NEXT: tilerelease
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; IPRA-NEXT: retq
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;
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; O0-LABEL: test_api:
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; O0: # %bb.0:
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; O0-NEXT: pushq %rbp
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; O0-NEXT: movq %rsp, %rbp
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; O0-NEXT: andq $-1024, %rsp # imm = 0xFC00
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; O0-NEXT: subq $4096, %rsp # imm = 0x1000
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; O0-NEXT: vpxor %xmm0, %xmm0, %xmm0
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; O0-NEXT: vmovups %zmm0, {{[0-9]+}}(%rsp)
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; O0-NEXT: movb $1, {{[0-9]+}}(%rsp)
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; O0-NEXT: movw %si, %cx
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; O0-NEXT: movw %cx, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; O0-NEXT: movw %di, %ax
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; O0-NEXT: movw %ax, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
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; O0-NEXT: movl $buf, %esi
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; O0-NEXT: movl $32, %edi
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; O0-NEXT: movw $8, %dx
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; O0-NEXT: # implicit-def: $al
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; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
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; O0-NEXT: movw %dx, {{[0-9]+}}(%rsp)
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; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; O0-NEXT: tileloadd (%rsi,%rdi), %tmm0
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; O0-NEXT: movl $64, %edi
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; O0-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
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; O0-NEXT: movw $8, %dx
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; O0-NEXT: tilestored %tmm0, (%rsi,%rdi)
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; O0-NEXT: movl $32, %esi
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; O0-NEXT: movl $buf+1024, %edx
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; O0-NEXT: movw $8, %ax
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; O0-NEXT: # implicit-def: $al
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; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
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; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
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; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; O0-NEXT: tileloadd (%rdx,%rsi), %tmm0
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; O0-NEXT: movl $64, %esi
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; O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
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; O0-NEXT: movw $8, %ax
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; O0-NEXT: tilestored %tmm0, (%rdx,%rsi)
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; O0-NEXT: vzeroupper
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; O0-NEXT: callq foo
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; O0-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %dx # 2-byte Reload
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; O0-NEXT: movw {{[-0-9]+}}(%r{{[sb]}}p), %ax # 2-byte Reload
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; O0-NEXT: movl $64, %edi
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; O0-NEXT: leaq {{[0-9]+}}(%rsp), %rsi
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; O0-NEXT: movw $8, %cx
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; O0-NEXT: # implicit-def: $cl
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; O0-NEXT: movb %cl, {{[0-9]+}}(%rsp)
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; O0-NEXT: movw %dx, {{[0-9]+}}(%rsp)
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; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; O0-NEXT: tileloadd (%rsi,%rdi), %tmm0
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; O0-NEXT: movw $8, %cx
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; O0-NEXT: tilemovrow $2, %tmm0, %zmm0
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; O0-NEXT: movl $64, %esi
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; O0-NEXT: leaq {{[0-9]+}}(%rsp), %rdx
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; O0-NEXT: movw $8, %cx
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; O0-NEXT: # implicit-def: $al
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; O0-NEXT: movb %al, {{[0-9]+}}(%rsp)
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; O0-NEXT: movw %cx, {{[0-9]+}}(%rsp)
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; O0-NEXT: ldtilecfg {{[0-9]+}}(%rsp)
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; O0-NEXT: tileloadd (%rdx,%rsi), %tmm0
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; O0-NEXT: movw $8, %cx
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; O0-NEXT: tilemovrow $2, %tmm0, %zmm1
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; O0-NEXT: vpaddd %zmm1, %zmm0, %zmm0
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; O0-NEXT: movq %rbp, %rsp
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; O0-NEXT: popq %rbp
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; O0-NEXT: tilerelease
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; O0-NEXT: retq
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%3 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 %0, i16 8, ptr @buf, i64 32)
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%4 = tail call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 %1, ptr getelementptr inbounds ([3072 x i8], ptr @buf, i64 0, i64 1024), i64 32)
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call void @foo()
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%5 = call <16 x i32> @llvm.x86.tilemovrow.internal(i16 8, i16 %1, x86_amx %4, i32 2)
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%6 = call <16 x i32> @llvm.x86.tilemovrow.internal(i16 %0, i16 8, x86_amx %3, i32 2)
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%7 = add <16 x i32> %5, %6
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ret <16 x i32> %7
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}
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declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, ptr, i64)
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declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
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declare void @llvm.x86.tilestored64.internal(i16, i16, ptr, i64, x86_amx)
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declare <16 x i32> @llvm.x86.tilemovrow.internal(i16, i16, x86_amx, i32)
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