derek.holloway
7502bf64a4
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238 lines
6.3 KiB
LLVM
238 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=i686-unknown -verify-machineinstrs < %s | FileCheck %s
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; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK-CGP %s
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; RUN: opt < %s -codegenprepare -cgpp-huge-func=0 -S -mtriple=x86_64-unknown-unknown | FileCheck --check-prefix=CHECK-CGP %s
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@A = global i32 zeroinitializer
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@B = global i32 zeroinitializer
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@C = global i32 zeroinitializer
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; Test that 'and' is sunk into bb0.
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define i32 @and_sink1(i32 %a, i1 %c) {
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; CHECK-LABEL: and_sink1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
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; CHECK-NEXT: je .LBB0_3
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; CHECK-NEXT: # %bb.1: # %bb0
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: testb $4, %al
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; CHECK-NEXT: movl $0, A
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; CHECK-NEXT: jne .LBB0_3
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; CHECK-NEXT: # %bb.2: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB0_3: # %bb2
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retl
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; CHECK-CGP-LABEL: @and_sink1(
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; CHECK-CGP-NOT: and i32
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%and = and i32 %a, 4
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br i1 %c, label %bb0, label %bb2
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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; CHECK-CGP-NEXT: store
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; CHECK-CGP-NEXT: br
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%cmp = icmp eq i32 %and, 0
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store i32 0, ptr @A
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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; Test that both 'and' and cmp get sunk to bb1.
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define i32 @and_sink2(i32 %a, i1 %c, i1 %c2) {
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; CHECK-LABEL: and_sink2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl $0, A
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; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
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; CHECK-NEXT: je .LBB1_5
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; CHECK-NEXT: # %bb.1: # %bb0.preheader
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; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB1_2: # %bb0
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movl $0, B
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; CHECK-NEXT: testb $1, %al
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; CHECK-NEXT: je .LBB1_5
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; CHECK-NEXT: # %bb.3: # %bb1
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; CHECK-NEXT: # in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: testb $4, %cl
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; CHECK-NEXT: movl $0, C
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; CHECK-NEXT: jne .LBB1_2
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; CHECK-NEXT: # %bb.4: # %bb2
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB1_5: # %bb3
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retl
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; CHECK-CGP-LABEL: @and_sink2(
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; CHECK-CGP-NOT: and i32
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%and = and i32 %a, 4
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store i32 0, ptr @A
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br i1 %c, label %bb0, label %bb3
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP-NOT: icmp
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%cmp = icmp eq i32 %and, 0
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store i32 0, ptr @B
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br i1 %c2, label %bb1, label %bb3
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bb1:
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; CHECK-CGP-LABEL: bb1:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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; CHECK-CGP-NEXT: store
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; CHECK-CGP-NEXT: br
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store i32 0, ptr @C
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br i1 %cmp, label %bb2, label %bb0
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bb2:
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ret i32 1
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bb3:
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ret i32 0
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}
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; Test that CodeGenPrepare doesn't get stuck in a loop sinking and hoisting a masked load.
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define i32 @and_sink3(i1 %c, ptr %p) {
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; CHECK-LABEL: and_sink3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
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; CHECK-NEXT: je .LBB2_3
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; CHECK-NEXT: # %bb.1: # %bb0
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movzbl (%eax), %eax
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: movl $0, A
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; CHECK-NEXT: je .LBB2_2
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; CHECK-NEXT: .LBB2_3: # %bb2
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB2_2: # %bb1
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-CGP-LABEL: @and_sink3(
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; CHECK-CGP: load i32
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; CHECK-CGP-NEXT: and i32
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%load = load i32, ptr %p
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%and = and i32 %load, 255
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br i1 %c, label %bb0, label %bb2
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP: icmp eq i32
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%cmp = icmp eq i32 %and, 0
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store i32 0, ptr @A
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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; Test that CodeGenPrepare sinks/duplicates non-immediate 'and'.
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define i32 @and_sink4(i32 %a, i32 %b, i1 %c) {
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; CHECK-LABEL: and_sink4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
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; CHECK-NEXT: je .LBB3_4
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; CHECK-NEXT: # %bb.1: # %bb0
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: testl %eax, %ecx
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; CHECK-NEXT: movl $0, A
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; CHECK-NEXT: jne .LBB3_4
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; CHECK-NEXT: # %bb.2: # %bb1
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; CHECK-NEXT: leal (%ecx,%eax), %edx
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; CHECK-NEXT: testl %eax, %ecx
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; CHECK-NEXT: movl %edx, B
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; CHECK-NEXT: je .LBB3_3
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; CHECK-NEXT: .LBB3_4: # %bb3
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB3_3: # %bb2
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-CGP-LABEL: @and_sink4(
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP-NOT: icmp
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%and = and i32 %a, %b
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%cmp = icmp eq i32 %and, 0
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br i1 %c, label %bb0, label %bb3
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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store i32 0, ptr @A
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br i1 %cmp, label %bb1, label %bb3
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bb1:
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; CHECK-CGP-LABEL: bb1:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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%add = add i32 %a, %b
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store i32 %add, ptr @B
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br i1 %cmp, label %bb2, label %bb3
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bb2:
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ret i32 1
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bb3:
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ret i32 0
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}
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; Test that CodeGenPrepare doesn't sink/duplicate non-immediate 'and'
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; when it would increase register pressure.
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define i32 @and_sink5(i32 %a, i32 %b, i32 %a2, i32 %b2, i1 %c) {
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; CHECK-LABEL: and_sink5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp)
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; CHECK-NEXT: je .LBB4_4
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; CHECK-NEXT: # %bb.1: # %bb0
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: andl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl $0, A
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; CHECK-NEXT: jne .LBB4_4
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; CHECK-NEXT: # %bb.2: # %bb1
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: testl %eax, %eax
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; CHECK-NEXT: movl %ecx, B
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; CHECK-NEXT: je .LBB4_3
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; CHECK-NEXT: .LBB4_4: # %bb3
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retl
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; CHECK-NEXT: .LBB4_3: # %bb2
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: retl
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; CHECK-CGP-LABEL: @and_sink5(
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; CHECK-CGP: and i32
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; CHECK-CGP-NOT: icmp
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%and = and i32 %a, %b
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%cmp = icmp eq i32 %and, 0
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br i1 %c, label %bb0, label %bb3
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP: icmp eq i32
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store i32 0, ptr @A
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br i1 %cmp, label %bb1, label %bb3
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bb1:
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; CHECK-CGP-LABEL: bb1:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP: icmp eq i32
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%add = add i32 %a2, %b2
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store i32 %add, ptr @B
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br i1 %cmp, label %bb2, label %bb3
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bb2:
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ret i32 1
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bb3:
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ret i32 0
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}
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