derek.holloway
7502bf64a4
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721 lines
24 KiB
LLVM
721 lines
24 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64
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;
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; 32-bit float to signed integer
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;
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declare i24 @llvm.fptosi.sat.i24.f32 (float)
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declare i48 @llvm.fptosi.sat.i48.f32 (float)
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define i24 @test_signed_i24_f32(float %f) nounwind {
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; X86-LABEL: test_signed_i24_f32:
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; X86: # %bb.0:
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; X86-NEXT: vcvttss2sis {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cmpl $-8388607, %eax # imm = 0xFF800001
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; X86-NEXT: movl $-8388608, %ecx # imm = 0xFF800000
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; X86-NEXT: cmovgel %eax, %ecx
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; X86-NEXT: cmpl $8388607, %ecx # imm = 0x7FFFFF
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; X86-NEXT: movl $8388607, %eax # imm = 0x7FFFFF
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; X86-NEXT: cmovll %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_i24_f32:
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; X64: # %bb.0:
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; X64-NEXT: vcvttss2sis %xmm0, %eax
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; X64-NEXT: cmpl $-8388607, %eax # imm = 0xFF800001
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; X64-NEXT: movl $-8388608, %ecx # imm = 0xFF800000
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; X64-NEXT: cmovgel %eax, %ecx
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; X64-NEXT: cmpl $8388607, %ecx # imm = 0x7FFFFF
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; X64-NEXT: movl $8388607, %eax # imm = 0x7FFFFF
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; X64-NEXT: cmovll %ecx, %eax
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; X64-NEXT: retq
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%x = call i24 @llvm.fptosi.sat.i24.f32(float %f)
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ret i24 %x
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}
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define i48 @test_signed_i48_f32(float %f) nounwind {
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; X86-LABEL: test_signed_i48_f32:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X86-NEXT: vcvttps2qq %xmm1, %xmm1
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; X86-NEXT: vmovd %xmm1, %esi
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-NEXT: cmovbl %ecx, %esi
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; X86-NEXT: vpextrd $1, %xmm1, %eax
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; X86-NEXT: movl $-32768, %edi # imm = 0x8000
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; X86-NEXT: cmovael %eax, %edi
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; X86-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-NEXT: movl $32767, %edx # imm = 0x7FFF
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; X86-NEXT: cmovbel %edi, %edx
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; X86-NEXT: movl $-1, %eax
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; X86-NEXT: cmovbel %esi, %eax
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; X86-NEXT: vucomiss %xmm0, %xmm0
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; X86-NEXT: cmovpl %ecx, %eax
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; X86-NEXT: cmovpl %ecx, %edx
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_i48_f32:
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; X64: # %bb.0:
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; X64-NEXT: vcvttss2sis %xmm0, %rcx
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; X64-NEXT: movabsq $-140737488355328, %rax # imm = 0xFFFF800000000000
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; X64-NEXT: cmpq %rax, %rcx
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; X64-NEXT: cmovgq %rcx, %rax
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; X64-NEXT: movabsq $140737488355327, %rcx # imm = 0x7FFFFFFFFFFF
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; X64-NEXT: cmpq %rcx, %rax
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; X64-NEXT: cmovgeq %rcx, %rax
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; X64-NEXT: retq
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%x = call i48 @llvm.fptosi.sat.i48.f32(float %f)
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ret i48 %x
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}
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declare i32 @llvm.fptosi.sat.i32.f32 (float)
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declare i64 @llvm.fptosi.sat.i64.f32 (float)
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define i32 @test_signed_i32_f32(float %f) nounwind {
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; X86-LABEL: test_signed_i32_f32:
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; X86: # %bb.0:
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; X86-NEXT: vcvttss2sis {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_i32_f32:
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; X64: # %bb.0:
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; X64-NEXT: vcvttss2sis %xmm0, %eax
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; X64-NEXT: retq
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%x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
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ret i32 %x
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}
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define i64 @test_signed_i64_f32(float %f) nounwind {
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; X86-LABEL: test_signed_i64_f32:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X86-NEXT: vcvttps2qq %xmm1, %xmm1
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; X86-NEXT: vmovd %xmm1, %esi
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-NEXT: cmovbl %ecx, %esi
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; X86-NEXT: vpextrd $1, %xmm1, %eax
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; X86-NEXT: movl $-2147483648, %edi # imm = 0x80000000
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; X86-NEXT: cmovael %eax, %edi
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; X86-NEXT: vucomiss {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
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; X86-NEXT: cmovbel %edi, %edx
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; X86-NEXT: movl $-1, %eax
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; X86-NEXT: cmovbel %esi, %eax
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; X86-NEXT: vucomiss %xmm0, %xmm0
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; X86-NEXT: cmovpl %ecx, %eax
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; X86-NEXT: cmovpl %ecx, %edx
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_i64_f32:
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; X64: # %bb.0:
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; X64-NEXT: vcvttss2sis %xmm0, %rax
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; X64-NEXT: retq
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%x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
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ret i64 %x
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}
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;
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; 64-bit float to signed integer
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;
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declare i24 @llvm.fptosi.sat.i24.f64 (double)
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declare i48 @llvm.fptosi.sat.i48.f64 (double)
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define i24 @test_signed_i24_f64(double %f) nounwind {
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; X86-LABEL: test_signed_i24_f64:
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; X86: # %bb.0:
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; X86-NEXT: vcvttsd2sis {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cmpl $-8388607, %eax # imm = 0xFF800001
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; X86-NEXT: movl $-8388608, %ecx # imm = 0xFF800000
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; X86-NEXT: cmovgel %eax, %ecx
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; X86-NEXT: cmpl $8388607, %ecx # imm = 0x7FFFFF
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; X86-NEXT: movl $8388607, %eax # imm = 0x7FFFFF
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; X86-NEXT: cmovll %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_i24_f64:
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; X64: # %bb.0:
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; X64-NEXT: vcvttsd2sis %xmm0, %eax
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; X64-NEXT: cmpl $-8388607, %eax # imm = 0xFF800001
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; X64-NEXT: movl $-8388608, %ecx # imm = 0xFF800000
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; X64-NEXT: cmovgel %eax, %ecx
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; X64-NEXT: cmpl $8388607, %ecx # imm = 0x7FFFFF
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; X64-NEXT: movl $8388607, %eax # imm = 0x7FFFFF
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; X64-NEXT: cmovll %ecx, %eax
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; X64-NEXT: retq
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%x = call i24 @llvm.fptosi.sat.i24.f64(double %f)
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ret i24 %x
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}
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define i48 @test_signed_i48_f64(double %f) nounwind {
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; X86-LABEL: test_signed_i48_f64:
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; X86: # %bb.0:
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; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X86-NEXT: vminmaxsd $21, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-NEXT: vminmaxsd $20, {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
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; X86-NEXT: vcvttpd2qq %xmm1, %xmm1
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; X86-NEXT: vmovd %xmm1, %eax
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: vucomisd %xmm0, %xmm0
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; X86-NEXT: cmovpl %ecx, %eax
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; X86-NEXT: vpextrd $1, %xmm1, %edx
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; X86-NEXT: cmovpl %ecx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_i48_f64:
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; X64: # %bb.0:
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; X64-NEXT: vcvttsd2sis %xmm0, %rcx
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; X64-NEXT: movabsq $-140737488355328, %rax # imm = 0xFFFF800000000000
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; X64-NEXT: cmpq %rax, %rcx
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; X64-NEXT: cmovgq %rcx, %rax
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; X64-NEXT: movabsq $140737488355327, %rcx # imm = 0x7FFFFFFFFFFF
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; X64-NEXT: cmpq %rcx, %rax
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; X64-NEXT: cmovgeq %rcx, %rax
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; X64-NEXT: retq
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%x = call i48 @llvm.fptosi.sat.i48.f64(double %f)
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ret i48 %x
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}
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declare i32 @llvm.fptosi.sat.i32.f64 (double)
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declare i64 @llvm.fptosi.sat.i64.f64 (double)
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define i32 @test_signed_i32_f64(double %f) nounwind {
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; X86-LABEL: test_signed_i32_f64:
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; X86: # %bb.0:
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; X86-NEXT: vcvttsd2sis {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_i32_f64:
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; X64: # %bb.0:
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; X64-NEXT: vcvttsd2sis %xmm0, %eax
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; X64-NEXT: retq
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%x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
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ret i32 %x
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}
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define i64 @test_signed_i64_f64(double %f) nounwind {
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; X86-LABEL: test_signed_i64_f64:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X86-NEXT: vcvttpd2qq %xmm0, %xmm1
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; X86-NEXT: vmovd %xmm1, %esi
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-NEXT: cmovbl %ecx, %esi
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; X86-NEXT: vpextrd $1, %xmm1, %eax
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; X86-NEXT: movl $-2147483648, %edi # imm = 0x80000000
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; X86-NEXT: cmovael %eax, %edi
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; X86-NEXT: vucomisd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
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; X86-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
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; X86-NEXT: cmovbel %edi, %edx
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; X86-NEXT: movl $-1, %eax
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; X86-NEXT: cmovbel %esi, %eax
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; X86-NEXT: vucomisd %xmm0, %xmm0
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; X86-NEXT: cmovpl %ecx, %eax
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; X86-NEXT: cmovpl %ecx, %edx
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_i64_f64:
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; X64: # %bb.0:
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; X64-NEXT: vcvttsd2sis %xmm0, %rax
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; X64-NEXT: retq
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%x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
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ret i64 %x
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}
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; VCVTTPD2DQS
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define <2 x i24> @test_signed_v2i24_v2f64(<2 x double> %d) nounwind {
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; X86-LABEL: test_signed_v2i24_v2f64:
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; X86: # %bb.0:
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; X86-NEXT: vcvttpd2qqs %xmm0, %xmm0
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; X86-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
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; X86-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_v2i24_v2f64:
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; X64: # %bb.0:
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; X64-NEXT: vcvttpd2qqs %xmm0, %xmm0
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; X64-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
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; X64-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
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; X64-NEXT: retq
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%x = call <2 x i24> @llvm.fptosi.sat.v2i24.v2f64(<2 x double> %d)
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ret <2 x i24> %x
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}
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define <4 x i24> @test_signed_v4i24_v4f64(<4 x double> %f) nounwind {
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; X86-LABEL: test_signed_v4i24_v4f64:
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; X86: # %bb.0:
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; X86-NEXT: vcvttpd2dqs %ymm0, %xmm0
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; X86-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
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; X86-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
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; X86-NEXT: vzeroupper
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; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_v4i24_v4f64:
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; X64: # %bb.0:
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; X64-NEXT: vcvttpd2dqs %ymm0, %xmm0
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; X64-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; X64-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; X64-NEXT: vzeroupper
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; X64-NEXT: retq
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%x = call <4 x i24> @llvm.fptosi.sat.v4i24.v4f64(<4 x double> %f)
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ret <4 x i24> %x
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}
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define <2 x i32> @test_signed_v2i32_v2f64(<2 x double> %d) nounwind {
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; CHECK-LABEL: test_signed_v2i32_v2f64:
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; CHECK: # %bb.0:
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|
; CHECK-NEXT: vcvttpd2dqs %xmm0, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%x = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %d)
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ret <2 x i32> %x
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}
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|
|
|
define <4 x i32> @test_signed_v4i32_v4f64(<4 x double> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v4i32_v4f64:
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|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: vcvttpd2dqs %ymm0, %xmm0
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|
; CHECK-NEXT: vzeroupper
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|
; CHECK-NEXT: ret{{[l|q]}}
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|
%x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f64(<4 x double> %f)
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ret <4 x i32> %x
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}
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; VCVTTPD2QQS
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define <2 x i48> @test_signed_v2i48_v2f64(<2 x double> %f) nounwind {
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|
; X86-LABEL: test_signed_v2i48_v2f64:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttpd2qqs %xmm0, %xmm0
|
|
; X86-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
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|
; X86-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
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|
; X86-NEXT: retl
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;
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; X64-LABEL: test_signed_v2i48_v2f64:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttpd2qqs %xmm0, %xmm0
|
|
; X64-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
|
|
; X64-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
|
|
; X64-NEXT: retq
|
|
%x = call <2 x i48> @llvm.fptosi.sat.v2i48.v2f64(<2 x double> %f)
|
|
ret <2 x i48> %x
|
|
}
|
|
|
|
define <4 x i48> @test_signed_v4i48_v4f64(<4 x double> %f) nounwind {
|
|
; X86-LABEL: test_signed_v4i48_v4f64:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttpd2qqs %ymm0, %ymm0
|
|
; X86-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
|
|
; X86-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_signed_v4i48_v4f64:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttpd2qqs %ymm0, %ymm0
|
|
; X64-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
|
|
; X64-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
|
|
; X64-NEXT: retq
|
|
%x = call <4 x i48> @llvm.fptosi.sat.v4i48.v4f64(<4 x double> %f)
|
|
ret <4 x i48> %x
|
|
}
|
|
|
|
define <2 x i64> @test_signed_v2i64_v2f64(<2 x double> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v2i64_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttpd2qqs %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double> %f)
|
|
ret <2 x i64> %x
|
|
}
|
|
|
|
define <4 x i64> @test_signed_v4i64_v4f64(<4 x double> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v4i64_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttpd2qqs %ymm0, %ymm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f64(<4 x double> %f)
|
|
ret <4 x i64> %x
|
|
}
|
|
|
|
; VCVTTPD2UDQS
|
|
define <2 x i24> @test_unsigned_v2i24_v2f64(<2 x double> %d) nounwind {
|
|
; X86-LABEL: test_unsigned_v2i24_v2f64:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttpd2uqqs %xmm0, %xmm0
|
|
; X86-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_unsigned_v2i24_v2f64:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttpd2uqqs %xmm0, %xmm0
|
|
; X64-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
|
|
; X64-NEXT: retq
|
|
%x = call <2 x i24> @llvm.fptoui.sat.v2i24.v2f64(<2 x double> %d)
|
|
ret <2 x i24> %x
|
|
}
|
|
|
|
define <4 x i24> @test_unsigned_v4i24_v4f64(<4 x double> %f) nounwind {
|
|
; X86-LABEL: test_unsigned_v4i24_v4f64:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttpd2udqs %ymm0, %xmm0
|
|
; X86-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
|
|
; X86-NEXT: vzeroupper
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_unsigned_v4i24_v4f64:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttpd2udqs %ymm0, %xmm0
|
|
; X64-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
|
|
; X64-NEXT: vzeroupper
|
|
; X64-NEXT: retq
|
|
%x = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f64(<4 x double> %f)
|
|
ret <4 x i24> %x
|
|
}
|
|
|
|
define <2 x i32> @test_unsigned_v2i32_v2f64(<2 x double> %d) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v2i32_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttpd2udqs %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %d)
|
|
ret <2 x i32> %x
|
|
}
|
|
|
|
define <4 x i32> @test_unsigned_v4i32_v4f64(<4 x double> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v4i32_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttpd2udqs %ymm0, %xmm0
|
|
; CHECK-NEXT: vzeroupper
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> %f)
|
|
ret <4 x i32> %x
|
|
}
|
|
|
|
; VCVTTPD2UQQS
|
|
define <2 x i48> @test_unsigned_v2i48_v2f64(<2 x double> %f) nounwind {
|
|
; X86-LABEL: test_unsigned_v2i48_v2f64:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttpd2uqqs %xmm0, %xmm0
|
|
; X86-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_unsigned_v2i48_v2f64:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttpd2uqqs %xmm0, %xmm0
|
|
; X64-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
|
|
; X64-NEXT: retq
|
|
%x = call <2 x i48> @llvm.fptoui.sat.v2i48.v2f64(<2 x double> %f)
|
|
ret <2 x i48> %x
|
|
}
|
|
|
|
define <4 x i48> @test_unsigned_v4i48_v4f64(<4 x double> %f) nounwind {
|
|
; X86-LABEL: test_unsigned_v4i48_v4f64:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttpd2uqqs %ymm0, %ymm0
|
|
; X86-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_unsigned_v4i48_v4f64:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttpd2uqqs %ymm0, %ymm0
|
|
; X64-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
|
|
; X64-NEXT: retq
|
|
%x = call <4 x i48> @llvm.fptoui.sat.v4i48.v4f64(<4 x double> %f)
|
|
ret <4 x i48> %x
|
|
}
|
|
|
|
define <2 x i64> @test_unsigned_v2i64_v2f64(<2 x double> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v2i64_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttpd2uqqs %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f64(<2 x double> %f)
|
|
ret <2 x i64> %x
|
|
}
|
|
|
|
define <4 x i64> @test_unsigned_v4i64_v4f64(<4 x double> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v4i64_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttpd2uqqs %ymm0, %ymm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f64(<4 x double> %f)
|
|
ret <4 x i64> %x
|
|
}
|
|
|
|
; VCVTTPS2DQS
|
|
define <4 x i24> @test_signed_v4i24_v4f32(<4 x float> %f) nounwind {
|
|
; X86-LABEL: test_signed_v4i24_v4f32:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttps2dqs %xmm0, %xmm0
|
|
; X86-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
|
|
; X86-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_signed_v4i24_v4f32:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttps2dqs %xmm0, %xmm0
|
|
; X64-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
|
|
; X64-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
|
|
; X64-NEXT: retq
|
|
%x = call <4 x i24> @llvm.fptosi.sat.v4i24.v4f32(<4 x float> %f)
|
|
ret <4 x i24> %x
|
|
}
|
|
|
|
define <8 x i24> @test_signed_v8i24_v8f32(<8 x float> %f) nounwind {
|
|
; X86-LABEL: test_signed_v8i24_v8f32:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttps2dqs %ymm0, %ymm0
|
|
; X86-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
|
|
; X86-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_signed_v8i24_v8f32:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttps2dqs %ymm0, %ymm0
|
|
; X64-NEXT: vpmaxsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
|
|
; X64-NEXT: vpminsd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
|
|
; X64-NEXT: retq
|
|
%x = call <8 x i24> @llvm.fptosi.sat.v8i24.v8f32(<8 x float> %f)
|
|
ret <8 x i24> %x
|
|
}
|
|
|
|
define <4 x i32> @test_signed_v4i32_v4f32(<4 x float> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v4i32_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttps2dqs %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %f)
|
|
ret <4 x i32> %x
|
|
}
|
|
|
|
define <8 x i32> @test_signed_v8i32_v8f32(<8 x float> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v8i32_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttps2dqs %ymm0, %ymm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <8 x i32> @llvm.fptosi.sat.v8i32.v8f32(<8 x float> %f)
|
|
ret <8 x i32> %x
|
|
}
|
|
|
|
; VCVTTPS2UDQS
|
|
define <4 x i24> @test_unsigned_v4i24_v4f32(<4 x float> %f) nounwind {
|
|
; X86-LABEL: test_unsigned_v4i24_v4f32:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttps2udqs %xmm0, %xmm0
|
|
; X86-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_unsigned_v4i24_v4f32:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttps2udqs %xmm0, %xmm0
|
|
; X64-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
|
|
; X64-NEXT: retq
|
|
%x = call <4 x i24> @llvm.fptoui.sat.v4i24.v4f32(<4 x float> %f)
|
|
ret <4 x i24> %x
|
|
}
|
|
|
|
define <8 x i24> @test_unsigned_v8i24_v8f32(<8 x float> %f) nounwind {
|
|
; X86-LABEL: test_unsigned_v8i24_v8f32:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttps2udqs %ymm0, %ymm0
|
|
; X86-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_unsigned_v8i24_v8f32:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttps2udqs %ymm0, %ymm0
|
|
; X64-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
|
|
; X64-NEXT: retq
|
|
%x = call <8 x i24> @llvm.fptoui.sat.v8i24.v8f32(<8 x float> %f)
|
|
ret <8 x i24> %x
|
|
}
|
|
|
|
define <4 x i32> @test_unsigned_v4i32_v4f32(<4 x float> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v4i32_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttps2udqs %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f32(<4 x float> %f)
|
|
ret <4 x i32> %x
|
|
}
|
|
|
|
define <8 x i32> @test_unsigned_v8i32_v8f32(<8 x float> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v8i32_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttps2udqs %ymm0, %ymm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <8 x i32> @llvm.fptoui.sat.v8i32.v8f32(<8 x float> %f)
|
|
ret <8 x i32> %x
|
|
}
|
|
|
|
; VCVTTPS2QQS
|
|
define <2 x i48> @test_signed_v2i48_v2f32(<2 x float> %f) nounwind {
|
|
; X86-LABEL: test_signed_v2i48_v2f32:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttps2qqs %xmm0, %ymm0
|
|
; X86-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
|
|
; X86-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
|
|
; X86-NEXT: vzeroupper
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_signed_v2i48_v2f32:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttps2qqs %xmm0, %ymm0
|
|
; X64-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
|
|
; X64-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
|
|
; X64-NEXT: vzeroupper
|
|
; X64-NEXT: retq
|
|
%x = call <2 x i48> @llvm.fptosi.sat.v2i48.v2f32(<2 x float> %f)
|
|
ret <2 x i48> %x
|
|
}
|
|
|
|
define <4 x i48> @test_signed_v4i48_v4f32(<4 x float> %f) nounwind {
|
|
; X86-LABEL: test_signed_v4i48_v4f32:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttps2qqs %xmm0, %ymm0
|
|
; X86-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
|
|
; X86-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_signed_v4i48_v4f32:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttps2qqs %xmm0, %ymm0
|
|
; X64-NEXT: vpmaxsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
|
|
; X64-NEXT: vpminsq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
|
|
; X64-NEXT: retq
|
|
%x = call <4 x i48> @llvm.fptosi.sat.v4i48.v4f32(<4 x float> %f)
|
|
ret <4 x i48> %x
|
|
}
|
|
|
|
define <2 x i64> @test_signed_v2i64_v2f32(<2 x float> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v2i64_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttps2qqs %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float> %f)
|
|
ret <2 x i64> %x
|
|
}
|
|
|
|
define <4 x i64> @test_signed_v4i64_v4f32(<4 x float> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v4i64_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttps2qqs %xmm0, %ymm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f32(<4 x float> %f)
|
|
ret <4 x i64> %x
|
|
}
|
|
|
|
; VCVTTPS2UQQS
|
|
define <2 x i48> @test_unsigned_v2i48_v2f32(<2 x float> %f) nounwind {
|
|
; X86-LABEL: test_unsigned_v2i48_v2f32:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttps2uqqs %xmm0, %ymm0
|
|
; X86-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}{1to2}, %xmm0, %xmm0
|
|
; X86-NEXT: vzeroupper
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_unsigned_v2i48_v2f32:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttps2uqqs %xmm0, %ymm0
|
|
; X64-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %xmm0
|
|
; X64-NEXT: vzeroupper
|
|
; X64-NEXT: retq
|
|
%x = call <2 x i48> @llvm.fptoui.sat.v2i48.v2f32(<2 x float> %f)
|
|
ret <2 x i48> %x
|
|
}
|
|
|
|
define <4 x i48> @test_unsigned_v4i48_v4f32(<4 x float> %f) nounwind {
|
|
; X86-LABEL: test_unsigned_v4i48_v4f32:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: vcvttps2uqqs %xmm0, %ymm0
|
|
; X86-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_unsigned_v4i48_v4f32:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: vcvttps2uqqs %xmm0, %ymm0
|
|
; X64-NEXT: vpminuq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %ymm0
|
|
; X64-NEXT: retq
|
|
%x = call <4 x i48> @llvm.fptoui.sat.v4i48.v4f32(<4 x float> %f)
|
|
ret <4 x i48> %x
|
|
}
|
|
|
|
define <2 x i64> @test_unsigned_v2i64_v2f32(<2 x float> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v2i64_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttps2uqqs %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float> %f)
|
|
ret <2 x i64> %x
|
|
}
|
|
|
|
define <4 x i64> @test_unsigned_v4i64_v4f32(<4 x float> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v4i64_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttps2uqqs %xmm0, %ymm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f32(<4 x float> %f)
|
|
ret <4 x i64> %x
|
|
}
|
|
|
|
; VCVTTBF162IUBS
|
|
define <8 x i8> @test_unsigned_v8i8_v8bf16(<8 x bfloat> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v8i8_v8bf16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttbf162iubs %xmm0, %xmm0
|
|
; CHECK-NEXT: vpmovwb %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <8 x i8> @llvm.fptoui.sat.v8i8.v8bf16(<8 x bfloat> %f)
|
|
ret <8 x i8> %x
|
|
}
|
|
|
|
define <16 x i8> @test_unsigned_v16i8_v16bf16(<16 x bfloat> %f) nounwind {
|
|
; CHECK-LABEL: test_unsigned_v16i8_v16bf16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttbf162iubs %ymm0, %ymm0
|
|
; CHECK-NEXT: vpmovwb %ymm0, %xmm0
|
|
; CHECK-NEXT: vzeroupper
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <16 x i8> @llvm.fptoui.sat.v16i8.v16bf16(<16 x bfloat> %f)
|
|
ret <16 x i8> %x
|
|
}
|
|
|
|
; VCVTTBF162IBS
|
|
define <8 x i8> @test_signed_v8i8_v8bf16(<8 x bfloat> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v8i8_v8bf16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttbf162ibs %xmm0, %xmm0
|
|
; CHECK-NEXT: vpmovwb %xmm0, %xmm0
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <8 x i8> @llvm.fptosi.sat.v8i8.v8bf16(<8 x bfloat> %f)
|
|
ret <8 x i8> %x
|
|
}
|
|
|
|
define <16 x i8> @test_signed_v16i8_v16bf16(<16 x bfloat> %f) nounwind {
|
|
; CHECK-LABEL: test_signed_v16i8_v16bf16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vcvttbf162ibs %ymm0, %ymm0
|
|
; CHECK-NEXT: vpmovwb %ymm0, %xmm0
|
|
; CHECK-NEXT: vzeroupper
|
|
; CHECK-NEXT: ret{{[l|q]}}
|
|
%x = call <16 x i8> @llvm.fptosi.sat.v16i8.v16bf16(<16 x bfloat> %f)
|
|
ret <16 x i8> %x
|
|
}
|