derek.holloway
7502bf64a4
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400 lines
20 KiB
LLVM
400 lines
20 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-apple-darwin -mattr=avx512f,avx512bw,avx512vl < %s | FileCheck %s
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; Skylake-avx512 target supports masked load/store for i8 and i16 vectors
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define <16 x i8> @test_mask_load_16xi8(<16 x i1> %mask, ptr %addr, <16 x i8> %val) {
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; CHECK-LABEL: test_mask_load_16xi8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
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; CHECK-NEXT: vpmovb2m %xmm0, %k1
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; CHECK-NEXT: vmovdqu8 (%rdi), %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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%res = call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %addr, i32 4, <16 x i1>%mask, <16 x i8> undef)
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ret <16 x i8> %res
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}
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declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr, i32, <16 x i1>, <16 x i8>)
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define <32 x i8> @test_mask_load_32xi8(<32 x i1> %mask, ptr %addr, <32 x i8> %val) {
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; CHECK-LABEL: test_mask_load_32xi8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0
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; CHECK-NEXT: vpmovb2m %ymm0, %k1
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; CHECK-NEXT: vpblendmb (%rdi), %ymm1, %ymm0 {%k1}
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; CHECK-NEXT: retq
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%res = call <32 x i8> @llvm.masked.load.v32i8.p0(ptr %addr, i32 4, <32 x i1>%mask, <32 x i8> %val)
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ret <32 x i8> %res
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}
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declare <32 x i8> @llvm.masked.load.v32i8.p0(ptr, i32, <32 x i1>, <32 x i8>)
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define <64 x i8> @test_mask_load_64xi8(<64 x i1> %mask, ptr %addr, <64 x i8> %val) {
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; CHECK-LABEL: test_mask_load_64xi8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %zmm0, %zmm0
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; CHECK-NEXT: vpmovb2m %zmm0, %k1
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; CHECK-NEXT: vpblendmb (%rdi), %zmm1, %zmm0 {%k1}
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; CHECK-NEXT: retq
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%res = call <64 x i8> @llvm.masked.load.v64i8.p0(ptr %addr, i32 4, <64 x i1>%mask, <64 x i8> %val)
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ret <64 x i8> %res
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}
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declare <64 x i8> @llvm.masked.load.v64i8.p0(ptr, i32, <64 x i1>, <64 x i8>)
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define <8 x i16> @test_mask_load_8xi16(<8 x i1> %mask, ptr %addr, <8 x i16> %val) {
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; CHECK-LABEL: test_mask_load_8xi16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $15, %xmm0, %xmm0
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; CHECK-NEXT: vpmovw2m %xmm0, %k1
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; CHECK-NEXT: vmovdqu16 (%rdi), %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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%res = call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %addr, i32 4, <8 x i1>%mask, <8 x i16> undef)
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ret <8 x i16> %res
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}
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declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32, <8 x i1>, <8 x i16>)
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define <16 x i16> @test_mask_load_16xi16(<16 x i1> %mask, ptr %addr, <16 x i16> %val) {
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; CHECK-LABEL: test_mask_load_16xi16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
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; CHECK-NEXT: vpmovb2m %xmm0, %k1
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; CHECK-NEXT: vmovdqu16 (%rdi), %ymm0 {%k1} {z}
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; CHECK-NEXT: retq
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%res = call <16 x i16> @llvm.masked.load.v16i16.p0(ptr %addr, i32 4, <16 x i1>%mask, <16 x i16> zeroinitializer)
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ret <16 x i16> %res
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}
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declare <16 x i16> @llvm.masked.load.v16i16.p0(ptr, i32, <16 x i1>, <16 x i16>)
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define <32 x i16> @test_mask_load_32xi16(<32 x i1> %mask, ptr %addr, <32 x i16> %val) {
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; CHECK-LABEL: test_mask_load_32xi16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0
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; CHECK-NEXT: vpmovb2m %ymm0, %k1
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; CHECK-NEXT: vpblendmw (%rdi), %zmm1, %zmm0 {%k1}
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; CHECK-NEXT: retq
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%res = call <32 x i16> @llvm.masked.load.v32i16.p0(ptr %addr, i32 4, <32 x i1>%mask, <32 x i16> %val)
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ret <32 x i16> %res
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}
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declare <32 x i16> @llvm.masked.load.v32i16.p0(ptr, i32, <32 x i1>, <32 x i16>)
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define void @test_mask_store_16xi8(<16 x i1> %mask, ptr %addr, <16 x i8> %val) {
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; CHECK-LABEL: test_mask_store_16xi8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
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; CHECK-NEXT: vpmovb2m %xmm0, %k1
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; CHECK-NEXT: vmovdqu8 %xmm1, (%rdi) {%k1}
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v16i8.p0(<16 x i8> %val, ptr %addr, i32 4, <16 x i1>%mask)
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ret void
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}
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declare void @llvm.masked.store.v16i8.p0(<16 x i8>, ptr, i32, <16 x i1>)
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define void @test_mask_store_32xi8(<32 x i1> %mask, ptr %addr, <32 x i8> %val) {
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; CHECK-LABEL: test_mask_store_32xi8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0
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; CHECK-NEXT: vpmovb2m %ymm0, %k1
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; CHECK-NEXT: vmovdqu8 %ymm1, (%rdi) {%k1}
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v32i8.p0(<32 x i8> %val, ptr %addr, i32 4, <32 x i1>%mask)
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ret void
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}
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declare void @llvm.masked.store.v32i8.p0(<32 x i8>, ptr, i32, <32 x i1>)
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define void @test_mask_store_64xi8(<64 x i1> %mask, ptr %addr, <64 x i8> %val) {
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; CHECK-LABEL: test_mask_store_64xi8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %zmm0, %zmm0
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; CHECK-NEXT: vpmovb2m %zmm0, %k1
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; CHECK-NEXT: vmovdqu8 %zmm1, (%rdi) {%k1}
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v64i8.p0(<64 x i8> %val, ptr %addr, i32 4, <64 x i1>%mask)
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ret void
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}
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declare void @llvm.masked.store.v64i8.p0(<64 x i8>, ptr, i32, <64 x i1>)
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define void @test_mask_store_8xi16(<8 x i1> %mask, ptr %addr, <8 x i16> %val) {
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; CHECK-LABEL: test_mask_store_8xi16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $15, %xmm0, %xmm0
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; CHECK-NEXT: vpmovw2m %xmm0, %k1
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; CHECK-NEXT: vmovdqu16 %xmm1, (%rdi) {%k1}
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v8i16.p0(<8 x i16> %val, ptr %addr, i32 4, <8 x i1>%mask)
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ret void
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}
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declare void @llvm.masked.store.v8i16.p0(<8 x i16>, ptr, i32, <8 x i1>)
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define void @test_mask_store_16xi16(<16 x i1> %mask, ptr %addr, <16 x i16> %val) {
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; CHECK-LABEL: test_mask_store_16xi16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
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; CHECK-NEXT: vpmovb2m %xmm0, %k1
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; CHECK-NEXT: vmovdqu16 %ymm1, (%rdi) {%k1}
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v16i16.p0(<16 x i16> %val, ptr %addr, i32 4, <16 x i1>%mask)
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ret void
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}
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declare void @llvm.masked.store.v16i16.p0(<16 x i16>, ptr, i32, <16 x i1>)
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define void @test_mask_store_32xi16(<32 x i1> %mask, ptr %addr, <32 x i16> %val) {
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; CHECK-LABEL: test_mask_store_32xi16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %ymm0, %ymm0
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; CHECK-NEXT: vpmovb2m %ymm0, %k1
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; CHECK-NEXT: vmovdqu16 %zmm1, (%rdi) {%k1}
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v32i16.p0(<32 x i16> %val, ptr %addr, i32 4, <32 x i1>%mask)
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ret void
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}
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declare void @llvm.masked.store.v32i16.p0(<32 x i16>, ptr, i32, <32 x i1>)
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; Make sure we scalarize masked loads of f16.
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define <16 x half> @test_mask_load_16xf16(<16 x i1> %mask, ptr %addr) {
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; CHECK-LABEL: test_mask_load_16xf16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
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; CHECK-NEXT: vpmovb2m %xmm0, %k1
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; CHECK-NEXT: vmovdqu16 (%rdi), %ymm0 {%k1} {z}
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; CHECK-NEXT: retq
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%res = call <16 x half> @llvm.masked.load.v16f16(ptr %addr, i32 4, <16 x i1>%mask, <16 x half> zeroinitializer)
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ret <16 x half> %res
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}
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declare <16 x half> @llvm.masked.load.v16f16(ptr, i32, <16 x i1>, <16 x half>)
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; Make sure we scalarize masked stores of f16.
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define void @test_mask_store_16xf16(<16 x i1> %mask, ptr %addr, <16 x half> %val) {
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; CHECK-LABEL: test_mask_store_16xf16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0
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; CHECK-NEXT: vpmovb2m %xmm0, %k1
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; CHECK-NEXT: vmovdqu16 %ymm1, (%rdi) {%k1}
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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call void @llvm.masked.store.v16f16.p0(<16 x half> %val, ptr %addr, i32 4, <16 x i1>%mask)
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ret void
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}
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declare void @llvm.masked.store.v16f16.p0(<16 x half>, ptr, i32, <16 x i1>)
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; PR198154
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define void @test_maskz_store_v192i8(ptr %p0, <192 x i1> %mask) nounwind {
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; CHECK-LABEL: test_maskz_store_v192i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0
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; CHECK-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; CHECK-NEXT: vmovd %esi, %xmm1
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; CHECK-NEXT: vpinsrb $1, %edx, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $2, %ecx, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $3, %r8d, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $4, %r9d, %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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; CHECK-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
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; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
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; CHECK-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm1
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; CHECK-NEXT: vpbroadcastb {{.*#+}} zmm0 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
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|
; CHECK-NEXT: vptestmb %zmm0, %zmm1, %k1
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|
; CHECK-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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|
; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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|
; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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|
; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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|
; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1
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|
; CHECK-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
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|
; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
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|
; CHECK-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
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|
; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm2, %xmm2
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|
; CHECK-NEXT: vmovd {{.*#+}} xmm3 = mem[0],zero,zero,zero
|
|
; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
|
|
; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1
|
|
; CHECK-NEXT: vptestmb %zmm0, %zmm1, %k2
|
|
; CHECK-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm1, %xmm1
|
|
; CHECK-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
|
; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
|
|
; CHECK-NEXT: vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
|
|
; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm2, %xmm2
|
|
; CHECK-NEXT: vmovd {{.*#+}} xmm3 = mem[0],zero,zero,zero
|
|
; CHECK-NEXT: vpinsrb $1, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $2, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $3, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $4, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $5, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm3, %xmm3
|
|
; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
|
|
; CHECK-NEXT: vinserti64x4 $1, %ymm1, %zmm2, %zmm1
|
|
; CHECK-NEXT: vptestmb %zmm0, %zmm1, %k3
|
|
; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
|
|
; CHECK-NEXT: vmovdqu8 %zmm0, 64(%rdi) {%k3}
|
|
; CHECK-NEXT: vmovdqu8 %zmm0, 128(%rdi) {%k2}
|
|
; CHECK-NEXT: vmovdqu8 %zmm0, (%rdi) {%k1}
|
|
; CHECK-NEXT: vzeroupper
|
|
; CHECK-NEXT: retq
|
|
tail call void @llvm.masked.store.v192i8.p0(<192 x i8> zeroinitializer, ptr %p0, <192 x i1> %mask)
|
|
ret void
|
|
}
|