derek.holloway
7502bf64a4
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276 lines
13 KiB
LLVM
276 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512fp16,avx512vl | FileCheck %s
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; FADD(acc, FMA(a, b, +0.0)) can be combined to FMA(a, b, acc) if the nsz flag set.
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define dso_local <32 x half> @test1(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfcmaddcph %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <32 x half> %a to <16 x float>
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%1 = bitcast <32 x half> %b to <16 x float>
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%2 = tail call nsz contract <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
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%3 = bitcast <16 x float> %2 to <32 x half>
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%add.i = fadd contract <32 x half> %3, %acc
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ret <32 x half> %add.i
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}
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define dso_local <32 x half> @test1_safe(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
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; CHECK-LABEL: test1_safe:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
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; CHECK-NEXT: vfcmaddcph %zmm2, %zmm1, %zmm3
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; CHECK-NEXT: vaddph %zmm0, %zmm3, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <32 x half> %a to <16 x float>
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%1 = bitcast <32 x half> %b to <16 x float>
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%2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
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%3 = bitcast <16 x float> %2 to <32 x half>
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%add.i = fadd contract <32 x half> %3, %acc
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ret <32 x half> %add.i
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}
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define dso_local <32 x half> @test2(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfmaddcph %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <32 x half> %a to <16 x float>
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%1 = bitcast <32 x half> %b to <16 x float>
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%2 = tail call nsz contract <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
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%3 = bitcast <16 x float> %2 to <32 x half>
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%add.i = fadd contract <32 x half> %3, %acc
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ret <32 x half> %add.i
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}
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define dso_local <32 x half> @test2_safe(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
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; CHECK-LABEL: test2_safe:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
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; CHECK-NEXT: vfmaddcph %zmm2, %zmm1, %zmm3
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; CHECK-NEXT: vaddph %zmm0, %zmm3, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <32 x half> %a to <16 x float>
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%1 = bitcast <32 x half> %b to <16 x float>
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%2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> zeroinitializer, i16 -1, i32 4)
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%3 = bitcast <16 x float> %2 to <32 x half>
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%add.i = fadd contract <32 x half> %3, %acc
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ret <32 x half> %add.i
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}
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define dso_local <16 x half> @test3(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfcmaddcph %ymm2, %ymm1, %ymm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <16 x half> %a to <8 x float>
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%1 = bitcast <16 x half> %b to <8 x float>
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%2 = tail call nsz contract <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
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%3 = bitcast <8 x float> %2 to <16 x half>
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%add.i = fadd contract <16 x half> %3, %acc
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ret <16 x half> %add.i
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}
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define dso_local <16 x half> @test3_safe(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
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; CHECK-LABEL: test3_safe:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
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; CHECK-NEXT: vfcmaddcph %ymm2, %ymm1, %ymm3
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; CHECK-NEXT: vaddph %ymm0, %ymm3, %ymm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <16 x half> %a to <8 x float>
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%1 = bitcast <16 x half> %b to <8 x float>
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%2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
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%3 = bitcast <8 x float> %2 to <16 x half>
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%add.i = fadd contract <16 x half> %3, %acc
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ret <16 x half> %add.i
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}
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define dso_local <16 x half> @test4(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfmaddcph %ymm2, %ymm1, %ymm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <16 x half> %a to <8 x float>
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%1 = bitcast <16 x half> %b to <8 x float>
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%2 = tail call nsz contract <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
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%3 = bitcast <8 x float> %2 to <16 x half>
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%add.i = fadd contract <16 x half> %3, %acc
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ret <16 x half> %add.i
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}
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define dso_local <16 x half> @test4_safe(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
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; CHECK-LABEL: test4_safe:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
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; CHECK-NEXT: vfmaddcph %ymm2, %ymm1, %ymm3
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; CHECK-NEXT: vaddph %ymm0, %ymm3, %ymm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <16 x half> %a to <8 x float>
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%1 = bitcast <16 x half> %b to <8 x float>
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%2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> zeroinitializer, i8 -1)
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%3 = bitcast <8 x float> %2 to <16 x half>
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%add.i = fadd contract <16 x half> %3, %acc
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ret <16 x half> %add.i
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}
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define dso_local <8 x half> @test5(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfcmaddcph %xmm2, %xmm1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <8 x half> %a to <4 x float>
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%1 = bitcast <8 x half> %b to <4 x float>
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%2 = tail call nsz contract <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
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%3 = bitcast <4 x float> %2 to <8 x half>
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%add.i = fadd contract <8 x half> %3, %acc
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ret <8 x half> %add.i
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}
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define dso_local <8 x half> @test5_safe(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: test5_safe:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
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; CHECK-NEXT: vfcmaddcph %xmm2, %xmm1, %xmm3
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; CHECK-NEXT: vaddph %xmm0, %xmm3, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <8 x half> %a to <4 x float>
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%1 = bitcast <8 x half> %b to <4 x float>
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%2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
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%3 = bitcast <4 x float> %2 to <8 x half>
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%add.i = fadd contract <8 x half> %3, %acc
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ret <8 x half> %add.i
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}
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define dso_local <8 x half> @test6(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfmaddcph %xmm2, %xmm1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <8 x half> %a to <4 x float>
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%1 = bitcast <8 x half> %b to <4 x float>
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%2 = tail call nsz contract <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
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%3 = bitcast <4 x float> %2 to <8 x half>
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%add.i = fadd contract <8 x half> %3, %acc
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ret <8 x half> %add.i
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}
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define dso_local <8 x half> @test6_safe(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: test6_safe:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vxorps %xmm3, %xmm3, %xmm3
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; CHECK-NEXT: vfmaddcph %xmm2, %xmm1, %xmm3
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; CHECK-NEXT: vaddph %xmm0, %xmm3, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <8 x half> %a to <4 x float>
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%1 = bitcast <8 x half> %b to <4 x float>
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%2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> zeroinitializer, i8 -1)
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%3 = bitcast <4 x float> %2 to <8 x half>
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%add.i = fadd contract <8 x half> %3, %acc
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ret <8 x half> %add.i
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}
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; FADD(acc, FMA(a, b, -0.0)) can be combined to FMA(a, b, acc) no matter if the nsz flag set.
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define dso_local <32 x half> @test13(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
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; CHECK-LABEL: test13:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfcmaddcph %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <32 x half> %a to <16 x float>
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%1 = bitcast <32 x half> %b to <16 x float>
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%2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i16 -1, i32 4)
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%3 = bitcast <16 x float> %2 to <32 x half>
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%add.i = fadd contract <32 x half> %3, %acc
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ret <32 x half> %add.i
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}
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define dso_local <32 x half> @test14(<32 x half> %acc, <32 x half> %a, <32 x half> %b) {
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; CHECK-LABEL: test14:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfmaddcph %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <32 x half> %a to <16 x float>
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%1 = bitcast <32 x half> %b to <16 x float>
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%2 = tail call contract <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float> %0, <16 x float> %1, <16 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i16 -1, i32 4)
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%3 = bitcast <16 x float> %2 to <32 x half>
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%add.i = fadd contract <32 x half> %3, %acc
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ret <32 x half> %add.i
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}
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define dso_local <16 x half> @test15(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
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; CHECK-LABEL: test15:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfcmaddcph %ymm2, %ymm1, %ymm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <16 x half> %a to <8 x float>
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%1 = bitcast <16 x half> %b to <8 x float>
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%2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
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%3 = bitcast <8 x float> %2 to <16 x half>
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%add.i = fadd contract <16 x half> %3, %acc
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ret <16 x half> %add.i
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}
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define dso_local <16 x half> @test16(<16 x half> %acc, <16 x half> %a, <16 x half> %b) {
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; CHECK-LABEL: test16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfmaddcph %ymm2, %ymm1, %ymm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <16 x half> %a to <8 x float>
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%1 = bitcast <16 x half> %b to <8 x float>
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%2 = tail call contract <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float> %0, <8 x float> %1, <8 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
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%3 = bitcast <8 x float> %2 to <16 x half>
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%add.i = fadd contract <16 x half> %3, %acc
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ret <16 x half> %add.i
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}
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define dso_local <8 x half> @test17(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: test17:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfcmaddcph %xmm2, %xmm1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <8 x half> %a to <4 x float>
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%1 = bitcast <8 x half> %b to <4 x float>
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%2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
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%3 = bitcast <4 x float> %2 to <8 x half>
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%add.i = fadd contract <8 x half> %3, %acc
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ret <8 x half> %add.i
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}
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define dso_local <8 x half> @test18(<8 x half> %acc, <8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: test18:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vfmaddcph %xmm2, %xmm1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = bitcast <8 x half> %a to <4 x float>
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%1 = bitcast <8 x half> %b to <4 x float>
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%2 = tail call contract <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float> %0, <4 x float> %1, <4 x float> <float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000, float 0xB790000000000000>, i8 -1)
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%3 = bitcast <4 x float> %2 to <8 x half>
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%add.i = fadd contract <8 x half> %3, %acc
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ret <8 x half> %add.i
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}
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declare <16 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)
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declare <16 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.512(<16 x float>, <16 x float>, <16 x float>, i16, i32 immarg)
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declare <8 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)
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declare <8 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.256(<8 x float>, <8 x float>, <8 x float>, i8)
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declare <4 x float> @llvm.x86.avx512fp16.mask.vfcmadd.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)
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declare <4 x float> @llvm.x86.avx512fp16.mask.vfmadd.cph.128(<4 x float>, <4 x float>, <4 x float>, i8)
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