derek.holloway
7502bf64a4
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344 lines
10 KiB
LLVM
344 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=CHECK,X64
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; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=CHECK,X86
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; Pin the peek-through paths in combineBTToBitOpFlag: the bit positions of
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; BT and the bit-modify can differ by an (and x, BW-1) mask or by trunc/zext
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; wrappers, and the combine should still fuse them into a single BTR/BTS/BTC.
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; (and x, 31) on the modify side, bare on the BT side.
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define i1 @fuse_and_mask_on_modify(ptr %word, i32 %position) nounwind {
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; X64-LABEL: fuse_and_mask_on_modify:
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; X64: # %bb.0:
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; X64-NEXT: movl (%rdi), %ecx
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; X64-NEXT: btcl %esi, %ecx
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; X64-NEXT: setb %al
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; X64-NEXT: movl %ecx, (%rdi)
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; X64-NEXT: retq
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;
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; X86-LABEL: fuse_and_mask_on_modify:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl (%ecx), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: btcl %eax, %edx
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; X86-NEXT: setb %al
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; X86-NEXT: movl %edx, (%ecx)
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; X86-NEXT: retl
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%ofs = and i32 %position, 31
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%bit = shl i32 1, %ofs
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%ld = load i32, ptr %word
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%res = xor i32 %ld, %bit
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%test = and i32 %ld, %bit
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%cmp = icmp ne i32 %test, 0
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store i32 %res, ptr %word
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ret i1 %cmp
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}
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; (and x, 63) on the BT side, bare on the modify side.
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define i1 @fuse_and_mask_on_bt(ptr %word, i64 %position) nounwind {
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; X64-LABEL: fuse_and_mask_on_bt:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %rcx
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; X64-NEXT: btsq %rsi, %rcx
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; X64-NEXT: setb %al
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; X64-NEXT: movq %rcx, (%rdi)
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; X64-NEXT: retq
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;
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; X86-LABEL: fuse_and_mask_on_bt:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl $1, %esi
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; X86-NEXT: xorl %edi, %edi
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; X86-NEXT: shldl %cl, %esi, %edi
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; X86-NEXT: shll %cl, %esi
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; X86-NEXT: testb $32, %cl
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; X86-NEXT: je .LBB1_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %esi, %edi
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; X86-NEXT: xorl %esi, %esi
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; X86-NEXT: .LBB1_2:
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: andl $32, %eax
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; X86-NEXT: shrl $3, %eax
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; X86-NEXT: movl (%edx,%eax), %eax
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; X86-NEXT: btl %ecx, %eax
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; X86-NEXT: setb %al
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; X86-NEXT: orl %esi, (%edx)
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; X86-NEXT: orl %edi, 4(%edx)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl
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%bit = shl i64 1, %position
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%ld = load i64, ptr %word
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%res = or i64 %ld, %bit
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%ofs = and i64 %position, 63
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%tbit = shl i64 1, %ofs
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%test = and i64 %ld, %tbit
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%cmp = icmp ne i64 %test, 0
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store i64 %res, ptr %word
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ret i1 %cmp
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}
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; ZERO_EXTEND wrapper on the bit position.
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define i1 @fuse_zext_pos(ptr %word, i32 %position) nounwind {
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; X64-LABEL: fuse_zext_pos:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $esi killed $esi def $rsi
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; X64-NEXT: movq (%rdi), %rcx
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; X64-NEXT: btrq %rsi, %rcx
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; X64-NEXT: setae %al
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; X64-NEXT: movq %rcx, (%rdi)
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; X64-NEXT: retq
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;
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; X86-LABEL: fuse_zext_pos:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl $1, %eax
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; X86-NEXT: xorl %esi, %esi
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; X86-NEXT: shldl %cl, %eax, %esi
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; X86-NEXT: shll %cl, %eax
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; X86-NEXT: testb $32, %cl
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; X86-NEXT: je .LBB2_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %eax, %esi
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; X86-NEXT: movl $0, %eax
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; X86-NEXT: .LBB2_2:
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; X86-NEXT: notl %esi
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; X86-NEXT: notl %eax
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; X86-NEXT: movl (%edx), %ebx
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; X86-NEXT: movl 4(%edx), %edi
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; X86-NEXT: movl %edi, %ebp
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; X86-NEXT: jne .LBB2_4
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; X86-NEXT: # %bb.3:
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; X86-NEXT: movl %ebx, %ebp
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; X86-NEXT: .LBB2_4:
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; X86-NEXT: andl %esi, %edi
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; X86-NEXT: andl %eax, %ebx
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; X86-NEXT: btl %ecx, %ebp
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; X86-NEXT: setae %al
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; X86-NEXT: movl %ebx, (%edx)
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; X86-NEXT: movl %edi, 4(%edx)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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%zext = zext i32 %position to i64
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%bit = shl i64 1, %zext
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%mask = xor i64 %bit, -1
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%ld = load i64, ptr %word
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%res = and i64 %ld, %mask
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%test = and i64 %ld, %bit
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%cmp = icmp eq i64 %test, 0
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store i64 %res, ptr %word
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ret i1 %cmp
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}
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; Negative: bit positions differ, BTC and BT must both remain.
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define i1 @no_fuse_diff_pos_xor(ptr %word, i32 %a, i32 %b) nounwind {
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; X64-LABEL: no_fuse_diff_pos_xor:
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; X64: # %bb.0:
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: movl %eax, %ecx
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; X64-NEXT: btcl %edx, %ecx
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; X64-NEXT: btl %esi, %eax
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; X64-NEXT: setb %al
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; X64-NEXT: movl %ecx, (%rdi)
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; X64-NEXT: retq
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;
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; X86-LABEL: no_fuse_diff_pos_xor:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl (%ecx), %edx
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; X86-NEXT: movl %edx, %esi
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; X86-NEXT: btcl %eax, %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: btl %eax, %edx
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; X86-NEXT: setb %al
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; X86-NEXT: movl %esi, (%ecx)
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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%bita = shl i32 1, %a
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%bitb = shl i32 1, %b
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%ld = load i32, ptr %word
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%res = xor i32 %ld, %bitb
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%test = and i32 %ld, %bita
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%cmp = icmp ne i32 %test, 0
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store i32 %res, ptr %word
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ret i1 %cmp
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}
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; Negative: bit positions differ, BTS and BT must both remain.
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define i1 @no_fuse_diff_pos_or(ptr %word, i64 %a, i64 %b) nounwind {
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; X64-LABEL: no_fuse_diff_pos_or:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: movq %rax, %rcx
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; X64-NEXT: btsq %rdx, %rcx
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; X64-NEXT: btq %rsi, %rax
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; X64-NEXT: setb %al
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; X64-NEXT: movq %rcx, (%rdi)
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; X64-NEXT: retq
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;
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; X86-LABEL: no_fuse_diff_pos_or:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl $1, %esi
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; X86-NEXT: xorl %edi, %edi
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; X86-NEXT: shldl %cl, %esi, %edi
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; X86-NEXT: shll %cl, %esi
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; X86-NEXT: testb $32, %cl
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; X86-NEXT: je .LBB4_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %esi, %edi
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; X86-NEXT: xorl %esi, %esi
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; X86-NEXT: .LBB4_2:
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; X86-NEXT: movl (%edx), %ebx
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; X86-NEXT: movl 4(%edx), %ecx
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; X86-NEXT: orl %ecx, %edi
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; X86-NEXT: orl %ebx, %esi
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; X86-NEXT: testb $32, %al
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; X86-NEXT: jne .LBB4_4
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; X86-NEXT: # %bb.3:
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; X86-NEXT: movl %ebx, %ecx
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; X86-NEXT: .LBB4_4:
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; X86-NEXT: btl %eax, %ecx
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; X86-NEXT: setb %al
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; X86-NEXT: movl %esi, (%edx)
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; X86-NEXT: movl %edi, 4(%edx)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: retl
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%bita = shl i64 1, %a
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%bitb = shl i64 1, %b
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%ld = load i64, ptr %word
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%res = or i64 %ld, %bitb
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%test = and i64 %ld, %bita
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%cmp = icmp ne i64 %test, 0
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store i64 %res, ptr %word
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ret i1 %cmp
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}
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; Negative: mask on the modify side drops a low bit (bit 0 of and-30 is clear),
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; so peek-through must leave the masked position in place and BTC/BT remain.
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define i1 @no_fuse_partial_mask_on_modify(ptr %word, i32 %position) nounwind {
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; X64-LABEL: no_fuse_partial_mask_on_modify:
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; X64: # %bb.0:
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: andb $30, %al
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; X64-NEXT: movl (%rdi), %ecx
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; X64-NEXT: movl %ecx, %edx
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; X64-NEXT: btcl %eax, %edx
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; X64-NEXT: andl $30, %esi
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; X64-NEXT: btl %esi, %ecx
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; X64-NEXT: setb %al
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; X64-NEXT: movl %edx, (%rdi)
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; X64-NEXT: retq
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;
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; X86-LABEL: no_fuse_partial_mask_on_modify:
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; X86: # %bb.0:
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %eax, %edx
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; X86-NEXT: andb $30, %dl
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; X86-NEXT: movl (%ecx), %esi
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; X86-NEXT: movl %esi, %edi
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; X86-NEXT: btcl %edx, %edi
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; X86-NEXT: andl $30, %eax
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; X86-NEXT: btl %eax, %esi
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; X86-NEXT: setb %al
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; X86-NEXT: movl %edi, (%ecx)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: retl
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%ofs = and i32 %position, 30
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%bit = shl i32 1, %ofs
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%ld = load i32, ptr %word
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%res = xor i32 %ld, %bit
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%test = and i32 %ld, %bit
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%cmp = icmp ne i32 %test, 0
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store i32 %res, ptr %word
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ret i1 %cmp
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}
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; Negative: bit positions differ, BTR and BT must both remain.
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define i1 @no_fuse_diff_pos_and(ptr %word, i64 %a, i64 %b) nounwind {
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; X64-LABEL: no_fuse_diff_pos_and:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: movq %rax, %rcx
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; X64-NEXT: btrq %rdx, %rcx
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; X64-NEXT: btq %rsi, %rax
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; X64-NEXT: setae %al
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; X64-NEXT: movq %rcx, (%rdi)
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; X64-NEXT: retq
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;
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; X86-LABEL: no_fuse_diff_pos_and:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebx
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; X86-NEXT: pushl %edi
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl $1, %esi
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; X86-NEXT: xorl %edi, %edi
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; X86-NEXT: shldl %cl, %esi, %edi
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; X86-NEXT: shll %cl, %esi
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; X86-NEXT: testb $32, %cl
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; X86-NEXT: je .LBB6_2
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; X86-NEXT: # %bb.1:
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; X86-NEXT: movl %esi, %edi
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; X86-NEXT: xorl %esi, %esi
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; X86-NEXT: .LBB6_2:
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; X86-NEXT: notl %edi
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; X86-NEXT: notl %esi
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; X86-NEXT: movl (%edx), %ebx
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; X86-NEXT: movl 4(%edx), %ecx
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; X86-NEXT: andl %ecx, %edi
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; X86-NEXT: andl %ebx, %esi
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; X86-NEXT: testb $32, %al
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; X86-NEXT: jne .LBB6_4
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; X86-NEXT: # %bb.3:
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; X86-NEXT: movl %ebx, %ecx
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; X86-NEXT: .LBB6_4:
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; X86-NEXT: btl %eax, %ecx
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; X86-NEXT: setae %al
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; X86-NEXT: movl %esi, (%edx)
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; X86-NEXT: movl %edi, 4(%edx)
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; X86-NEXT: popl %esi
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; X86-NEXT: popl %edi
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; X86-NEXT: popl %ebx
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; X86-NEXT: retl
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%bita = shl i64 1, %a
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%bitb = shl i64 1, %b
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%notb = xor i64 %bitb, -1
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%ld = load i64, ptr %word
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%res = and i64 %ld, %notb
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%test = and i64 %ld, %bita
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%cmp = icmp eq i64 %test, 0
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store i64 %res, ptr %word
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ret i1 %cmp
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}
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