derek.holloway
7502bf64a4
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371 lines
13 KiB
LLVM
371 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; FIXME(ndesaulniers): get this test to pass with -verify-machineinstrs
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; enabled. https://github.com/llvm/llvm-project/issues/60827
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; RUN: llc -mtriple=x86_64-linux-gnu %s -o - -stop-after=finalize-isel \
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; RUN: -verify-machineinstrs=0 -start-before=x86-isel | FileCheck %s
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; One virtual register, w/o phi
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define i32 @test0() {
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; CHECK-LABEL: name: test0
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: INLINEASM_BR &"", attdialect, regdef:GR32_NOREX2, def %1, imm, %bb.2
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %1
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; CHECK-NEXT: JMP_1 %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.cleanup:
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; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
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; CHECK-NEXT: $eax = COPY [[MOV32ri]]
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; CHECK-NEXT: RET 0, $eax
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.z.split (inlineasm-br-indirect-target):
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; CHECK-NEXT: $eax = COPY %1
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; CHECK-NEXT: RET 0, $eax
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%direct = callbr i32 asm "", "=r,!i"()
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to label %cleanup [label %z.split]
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cleanup:
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ret i32 42
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z.split:
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%indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
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ret i32 %indirect
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}
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; One virtual register, w/ phi
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define i32 @test1() {
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; CHECK-LABEL: name: test1
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
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; CHECK-NEXT: INLINEASM_BR &"", attdialect, regdef:GR32_NOREX2, def %4, imm, %bb.1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %4
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.z.split (inlineasm-br-indirect-target):
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.cleanup:
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY1]], %bb.1
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; CHECK-NEXT: $eax = COPY [[PHI]]
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; CHECK-NEXT: RET 0, $eax
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entry:
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%direct = callbr i32 asm "", "=r,!i"()
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to label %cleanup [label %z.split]
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z.split:
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%indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
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br label %cleanup
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cleanup:
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%retval.0 = phi i32 [ %indirect, %z.split ], [ 42, %entry ]
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ret i32 %retval.0
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}
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; Two virtual registers
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define i32 @test2() {
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; CHECK-LABEL: name: test2
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
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; CHECK-NEXT: INLINEASM_BR &"", attdialect, regdef:GR32_NOREX2, def %5, regdef:GR32_NOREX2, def %6, imm, %bb.1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %6
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %5
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.z.split (inlineasm-br-indirect-target):
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY %5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.cleanup:
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY2]], %bb.1
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; CHECK-NEXT: $eax = COPY [[PHI]]
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; CHECK-NEXT: RET 0, $eax
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entry:
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%direct = callbr { i32, i32 } asm "", "=r,=r,!i"()
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to label %cleanup [label %z.split]
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z.split:
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%indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 } %direct)
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%asmresult2 = extractvalue { i32, i32 } %indirect, 0
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br label %cleanup
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cleanup:
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%retval.0 = phi i32 [ %asmresult2, %z.split ], [ 42, %entry ]
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ret i32 %retval.0
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}
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; One physical register
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define i32 @test3() {
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; CHECK-LABEL: name: test3
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
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; CHECK-NEXT: INLINEASM_BR &"", attdialect, regdef, implicit-def $ebx, imm, %bb.1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $ebx
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]]
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.z.split (inlineasm-br-indirect-target):
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $ebx
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $ebx
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY2]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.cleanup:
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY3]], %bb.1
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; CHECK-NEXT: $eax = COPY [[PHI]]
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; CHECK-NEXT: RET 0, $eax
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entry:
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%direct = callbr i32 asm "", "={bx},!i"()
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to label %cleanup [label %z.split]
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z.split:
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%indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
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br label %cleanup
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cleanup:
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%retval.0 = phi i32 [ %indirect, %z.split ], [ 42, %entry ]
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ret i32 %retval.0
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}
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; Two physical registers
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define i32 @test4() {
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; CHECK-LABEL: name: test4
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
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; CHECK-NEXT: INLINEASM_BR &"", attdialect, regdef, implicit-def $ebx, regdef, implicit-def $edx, imm, %bb.1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $ebx
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edx
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY1]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY [[COPY]]
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.z.split (inlineasm-br-indirect-target):
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $ebx, $edx
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY $ebx
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr32 = COPY [[COPY4]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.cleanup:
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32ri]], %bb.0, [[COPY5]], %bb.1
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; CHECK-NEXT: $eax = COPY [[PHI]]
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; CHECK-NEXT: RET 0, $eax
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entry:
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%direct = callbr { i32, i32 } asm "", "={bx},={dx},!i"()
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to label %cleanup [label %z.split]
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z.split:
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%indirect = call { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 } %direct)
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%asmresult2 = extractvalue { i32, i32 } %indirect, 0
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br label %cleanup
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cleanup:
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%retval.0 = phi i32 [ %asmresult2, %z.split ], [ 42, %entry ]
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ret i32 %retval.0
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}
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; Test the same destination appearing in the direct/fallthrough branch as the
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; indirect branch. Physreg.
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define i32 @test5() {
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; CHECK-LABEL: name: test5
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: INLINEASM_BR &"# $0", attdialect, regdef, implicit-def $ebx, imm, %bb.1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $ebx
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]]
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; CHECK-NEXT: JMP_1 %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.cleanup (inlineasm-br-indirect-target):
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; CHECK-NEXT: liveins: $ebx
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $ebx
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; CHECK-NEXT: $eax = COPY [[COPY2]]
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; CHECK-NEXT: RET 0, $eax
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entry:
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%direct = callbr i32 asm "# $0", "={bx},!i"()
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to label %cleanup [label %cleanup]
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cleanup:
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%indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
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ret i32 %indirect
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}
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; "The Devil's cross" (i.e. two asm goto with conflicting physreg constraints
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; going to the same destination) as expressed by clang.
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define i64 @test6() {
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; CHECK-LABEL: name: test6
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.3(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: INLINEASM_BR &"", attdialect, regdef, implicit-def $rdx, imm, %bb.3
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdx
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY [[COPY]]
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; CHECK-NEXT: JMP_1 %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.asm.fallthrough:
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; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.4(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: INLINEASM_BR &"", attdialect, regdef, implicit-def $rbx, imm, %bb.4
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rbx
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr64 = COPY [[COPY2]]
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.foo:
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gr64 = PHI %3, %bb.3, [[COPY3]], %bb.1, %4, %bb.4
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; CHECK-NEXT: $rax = COPY [[PHI]]
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; CHECK-NEXT: RET 0, $rax
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.foo.split (inlineasm-br-indirect-target):
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $rdx
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = COPY $rdx
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr64 = COPY [[COPY4]]
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4.foo.split2 (inlineasm-br-indirect-target):
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $rbx
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY6:%[0-9]+]]:gr64 = COPY $rbx
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; CHECK-NEXT: [[COPY7:%[0-9]+]]:gr64 = COPY [[COPY6]]
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; CHECK-NEXT: JMP_1 %bb.2
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entry:
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%0 = callbr i64 asm "", "={dx},!i"()
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to label %asm.fallthrough [label %foo.split]
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asm.fallthrough:
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%1 = callbr i64 asm "", "={bx},!i"()
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to label %foo [label %foo.split2]
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foo:
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%x.0 = phi i64 [ %3, %foo.split2 ], [ %2, %foo.split ], [ %1, %asm.fallthrough ]
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ret i64 %x.0
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foo.split:
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%2 = call i64 @llvm.callbr.landingpad.i64(i64 %0)
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br label %foo
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foo.split2:
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%3 = call i64 @llvm.callbr.landingpad.i64(i64 %1)
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br label %foo
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}
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; Test a callbr looping back on itself.
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define i32 @test7() {
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; CHECK-LABEL: name: test7
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.retry:
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; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.3(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[DEF]], %bb.0, %2, %bb.3
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY [[PHI]]
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; CHECK-NEXT: INLINEASM_BR &"", attdialect, regdef, implicit-def $edx, reguse tiedto:$0, [[COPY]](tied-def 3), imm, %bb.3
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $edx
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY [[COPY1]]
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; CHECK-NEXT: JMP_1 %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.asm.fallthrough:
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; CHECK-NEXT: $eax = COPY [[COPY2]]
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; CHECK-NEXT: RET 0, $eax
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.retry.split (inlineasm-br-indirect-target):
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $edx
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY [[COPY3]]
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; CHECK-NEXT: JMP_1 %bb.1
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entry:
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br label %retry
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retry:
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%x.0 = phi i32 [ undef, %entry ], [ %1, %retry.split ]
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%0 = callbr i32 asm "", "={dx},0,!i"(i32 %x.0)
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to label %asm.fallthrough [label %retry.split]
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asm.fallthrough:
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ret i32 %0
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retry.split:
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%1 = call i32 @llvm.callbr.landingpad.i32(i32 %0)
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br label %retry
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}
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; Test the same destination appearing in the direct/fallthrough branch as the
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; indirect branch. Same as test5 but with a virtreg rather than a physreg
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; constraint.
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define i32 @test8() {
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; CHECK-LABEL: name: test8
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: INLINEASM_BR &"# $0", attdialect, regdef:GR32_NOREX2, def %1, imm, %bb.1
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %1
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; CHECK-NEXT: JMP_1 %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.cleanup (inlineasm-br-indirect-target):
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; CHECK-NEXT: $eax = COPY %1
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; CHECK-NEXT: RET 0, $eax
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entry:
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%direct = callbr i32 asm "# $0", "=r,!i"()
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to label %cleanup [label %cleanup]
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cleanup:
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%indirect = call i32 @llvm.callbr.landingpad.i32(i32 %direct)
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ret i32 %indirect
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}
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define i64 @condition_code() {
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; CHECK-LABEL: name: condition_code
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; CHECK: bb.0 (%ir-block.0):
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; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: INLINEASM_BR &"", maystore attdialect, regdef:GR32, def %1, imm, %bb.2
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; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
|
|
; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr]]
|
|
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOVZX32rr8_]], %subreg.sub_32bit
|
|
; CHECK-NEXT: JMP_1 %bb.1
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.1.b:
|
|
; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]]
|
|
; CHECK-NEXT: RET 0, $rax
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: bb.2.c (inlineasm-br-indirect-target):
|
|
; CHECK-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
|
|
; CHECK-NEXT: [[MOVZX32rr8_1:%[0-9]+]]:gr32 = MOVZX32rr8 killed [[SETCCr1]]
|
|
; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64 = SUBREG_TO_REG killed [[MOVZX32rr8_1]], %subreg.sub_32bit
|
|
; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG1]]
|
|
; CHECK-NEXT: RET 0, $rax
|
|
%a = callbr i64 asm "", "={@ccz},!i"()
|
|
to label %b [label %c]
|
|
|
|
b:
|
|
ret i64 %a
|
|
|
|
c:
|
|
%1 = call i64 @llvm.callbr.landingpad.i64(i64 %a)
|
|
ret i64 %1
|
|
}
|
|
|
|
declare i64 @llvm.callbr.landingpad.i64(i64)
|
|
declare i32 @llvm.callbr.landingpad.i32(i32)
|
|
declare { i32, i32 } @llvm.callbr.landingpad.sl_i32i32s({ i32, i32 })
|