derek.holloway
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59 lines
3.2 KiB
YAML
59 lines
3.2 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=x86_64 -run-pass=register-coalescer -o - %s | FileCheck %s
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# When the coalescer removes the COPY by commuting the operands of the AND, it should also update the `implicit-def` of the destination register.
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---
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name: implicit_def_dst
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: implicit_def_dst
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; CHECK: [[MOV64rm:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
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; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
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; CHECK-NEXT: [[MOV64rm:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = AND32rr [[MOV64rm]].sub_32bit, [[MOV64rm1]].sub_32bit, implicit-def dead $eflags, implicit-def [[MOV64rm]]
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; CHECK-NEXT: RET 0, implicit [[MOV64rm]]
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%0:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
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%1:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
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%1.sub_32bit:gr64_with_sub_8bit = AND32rr %1.sub_32bit:gr64_with_sub_8bit, %0.sub_32bit:gr64_with_sub_8bit, implicit-def dead $eflags, implicit-def %1:gr64_with_sub_8bit
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%0:gr64_with_sub_8bit = COPY %1:gr64_with_sub_8bit
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RET 0, implicit %0
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...
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# In case the MIR for some reason contains more than one implicit-def of the destination reg, then all should be updated.
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---
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name: two_implicit_defs_dst
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: two_implicit_defs_dst
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; CHECK: [[MOV64rm:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
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; CHECK-NEXT: [[MOV64rm1:%[0-9]+]]:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
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; CHECK-NEXT: [[MOV64rm:%[0-9]+]].sub_32bit:gr64_with_sub_8bit = AND32rr [[MOV64rm]].sub_32bit, [[MOV64rm1]].sub_32bit, implicit-def dead $eflags, implicit-def [[MOV64rm]], implicit-def [[MOV64rm]]
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; CHECK-NEXT: RET 0, implicit [[MOV64rm]]
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%0:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
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%1:gr64_with_sub_8bit = MOV64rm $noreg, 1, $noreg, 0, $noreg :: (load (s64) from `ptr null`)
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%1.sub_32bit:gr64_with_sub_8bit = AND32rr %1.sub_32bit:gr64_with_sub_8bit, %0.sub_32bit:gr64_with_sub_8bit, implicit-def dead $eflags, implicit-def %1:gr64_with_sub_8bit, implicit-def %1:gr64_with_sub_8bit
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%0:gr64_with_sub_8bit = COPY %1:gr64_with_sub_8bit
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RET 0, implicit %0
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...
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# Commuting instruction with 3 ops is handled correctly.
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---
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name: commuting_3_ops
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $ymm0, $ymm1
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; CHECK-LABEL: name: commuting_3_ops
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; CHECK: liveins: $ymm0, $ymm1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vr256 = COPY $ymm1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256 = contract nofpexcept VFMADD213PSYr [[COPY1]], [[COPY]], [[COPY]], implicit $mxcsr
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; CHECK-NEXT: RET 0, implicit [[COPY1]]
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%0:vr256 = COPY $ymm1
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%1:vr256 = COPY $ymm0
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%0:vr256 = contract nofpexcept VFMADD231PSYr %0:vr256, %0:vr256, %1:vr256, implicit $mxcsr
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%1:vr256 = COPY %0:vr256
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RET 0, implicit %1
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...
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