derek.holloway
7502bf64a4
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366 lines
14 KiB
LLVM
366 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX512
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;
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; NOTE: this is generated by utils/update_llc_test_checks.py but we can't check NAN types (PR30443),
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; so we need to edit it to remove the NAN constant comments
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;
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; copysign(x, c1) -> fabs(x) iff ispos(c1)
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define <4 x float> @combine_vec_fcopysign_pos_constant0(<4 x float> %x) {
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; SSE-LABEL: combine_vec_fcopysign_pos_constant0:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_pos_constant0:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_pos_constant0:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>)
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ret <4 x float> %1
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}
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define <4 x float> @combine_vec_fcopysign_pos_constant1(<4 x float> %x) {
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; SSE-LABEL: combine_vec_fcopysign_pos_constant1:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_pos_constant1:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_pos_constant1:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> <float 0.0, float 2.0, float 4.0, float 8.0>)
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ret <4 x float> %1
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}
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define <4 x float> @combine_vec_fcopysign_fabs_sgn(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fabs_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_fabs_sgn:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [NaN,NaN,NaN,NaN]
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; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_fabs_sgn:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %1)
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ret <4 x float> %2
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}
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; copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
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define <4 x float> @combine_vec_fcopysign_neg_constant0(<4 x float> %x) {
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; SSE-LABEL: combine_vec_fcopysign_neg_constant0:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_neg_constant0:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_neg_constant0:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> <float -2.0, float -2.0, float -2.0, float -2.0>)
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ret <4 x float> %1
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}
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define <4 x float> @combine_vec_fcopysign_neg_constant1(<4 x float> %x) {
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; SSE-LABEL: combine_vec_fcopysign_neg_constant1:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_neg_constant1:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_neg_constant1:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> <float -0.0, float -2.0, float -4.0, float -8.0>)
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ret <4 x float> %1
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}
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define <4 x float> @combine_vec_fcopysign_fneg_fabs_sgn(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fneg_fabs_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_fneg_fabs_sgn:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_fneg_fabs_sgn:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %y)
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%2 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %1
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%3 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %2)
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ret <4 x float> %3
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}
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; copysign(fabs(x), y) -> copysign(x, y)
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define <4 x float> @combine_vec_fcopysign_fabs_mag(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fabs_mag:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_fabs_mag:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_fabs_mag:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (m32bcst & (xmm0 ^ xmm1))
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %1, <4 x float> %y)
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ret <4 x float> %2
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}
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; copysign(fneg(x), y) -> copysign(x, y)
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define <4 x float> @combine_vec_fcopysign_fneg_mag(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fneg_mag:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_fneg_mag:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_fneg_mag:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (m32bcst & (xmm0 ^ xmm1))
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; AVX512-NEXT: retq
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%1 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %x
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %1, <4 x float> %y)
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ret <4 x float> %2
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}
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; copysign(copysign(x,z), y) -> copysign(x, y)
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define <4 x float> @combine_vec_fcopysign_fcopysign_mag(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; SSE-LABEL: combine_vec_fcopysign_fcopysign_mag:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_fcopysign_mag:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX2-NEXT: vandps %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_fcopysign_mag:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (m32bcst & (xmm0 ^ xmm1))
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %z)
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %1, <4 x float> %y)
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ret <4 x float> %2
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}
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; copysign(x, copysign(y,z)) -> copysign(x, z)
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define <4 x float> @combine_vec_fcopysign_fcopysign_sgn(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
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; SSE-LABEL: combine_vec_fcopysign_fcopysign_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
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; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: orps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_fcopysign_sgn:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX2-NEXT: vandps %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
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; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_fcopysign_sgn:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm1
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; AVX512-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (m32bcst & (xmm0 ^ xmm1))
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; AVX512-NEXT: retq
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%1 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %y, <4 x float> %z)
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%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %1)
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ret <4 x float> %2
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}
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; copysign(x, fp_extend(y)) -> copysign(x, y)
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define <4 x double> @combine_vec_fcopysign_fpext_sgn(<4 x double> %x, <4 x float> %y) {
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; SSE-LABEL: combine_vec_fcopysign_fpext_sgn:
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; SSE: # %bb.0:
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; SSE-NEXT: cvtps2pd %xmm2, %xmm3
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; SSE-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
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; SSE-NEXT: cvtps2pd %xmm2, %xmm2
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; SSE-NEXT: movaps {{.*#+}} xmm4 = [NaN,NaN]
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; SSE-NEXT: andps %xmm4, %xmm0
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; SSE-NEXT: movaps %xmm4, %xmm5
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; SSE-NEXT: andnps %xmm3, %xmm5
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; SSE-NEXT: orps %xmm5, %xmm0
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; SSE-NEXT: andps %xmm4, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm4
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; SSE-NEXT: orps %xmm4, %xmm1
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; SSE-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_fcopysign_fpext_sgn:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vcvtps2pd %xmm1, %ymm1
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; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
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; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vbroadcastsd {{.*#+}} ymm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
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; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1
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; AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_fcopysign_fpext_sgn:
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; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vcvtps2pd %xmm1, %ymm1
|
|
; AVX512-NEXT: vpternlogq {{.*#+}} ymm0 = ymm1 ^ (m64bcst & (ymm0 ^ ymm1))
|
|
; AVX512-NEXT: retq
|
|
%1 = fpext <4 x float> %y to <4 x double>
|
|
%2 = call <4 x double> @llvm.copysign.v4f64(<4 x double> %x, <4 x double> %1)
|
|
ret <4 x double> %2
|
|
}
|
|
|
|
; copysign(x, fp_round(y)) -> copysign(x, y)
|
|
define <4 x float> @combine_vec_fcopysign_fptrunc_sgn(<4 x float> %x, <4 x double> %y) {
|
|
; SSE-LABEL: combine_vec_fcopysign_fptrunc_sgn:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: cvtpd2ps %xmm2, %xmm2
|
|
; SSE-NEXT: cvtpd2ps %xmm1, %xmm1
|
|
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
|
; SSE-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
|
; SSE-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
|
|
; SSE-NEXT: orpd %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX2-LABEL: combine_vec_fcopysign_fptrunc_sgn:
|
|
; AVX2: # %bb.0:
|
|
; AVX2-NEXT: vcvtpd2ps %ymm1, %xmm1
|
|
; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [NaN,NaN,NaN,NaN]
|
|
; AVX2-NEXT: vandpd %xmm2, %xmm0, %xmm0
|
|
; AVX2-NEXT: vbroadcastss {{.*#+}} xmm2 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
|
|
; AVX2-NEXT: vandpd %xmm2, %xmm1, %xmm1
|
|
; AVX2-NEXT: vorpd %xmm1, %xmm0, %xmm0
|
|
; AVX2-NEXT: vzeroupper
|
|
; AVX2-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: combine_vec_fcopysign_fptrunc_sgn:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vcvtpd2ps %ymm1, %xmm1
|
|
; AVX512-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (m32bcst & (xmm0 ^ xmm1))
|
|
; AVX512-NEXT: vzeroupper
|
|
; AVX512-NEXT: retq
|
|
%1 = fptrunc <4 x double> %y to <4 x float>
|
|
%2 = call <4 x float> @llvm.copysign.v4f32(<4 x float> %x, <4 x float> %1)
|
|
ret <4 x float> %2
|
|
}
|
|
|
|
define double @PR136368(double %x) {
|
|
; SSE-LABEL: PR136368:
|
|
; SSE: # %bb.0:
|
|
; SSE-NEXT: movapd {{.*#+}} xmm1 = [NaN,NaN]
|
|
; SSE-NEXT: movapd %xmm0, %xmm2
|
|
; SSE-NEXT: andpd %xmm1, %xmm2
|
|
; SSE-NEXT: movsd {{.*#+}} xmm3 = [1.5707963267948966E+0,0.0E+0]
|
|
; SSE-NEXT: movapd %xmm3, %xmm4
|
|
; SSE-NEXT: cmpltsd %xmm2, %xmm4
|
|
; SSE-NEXT: andpd %xmm3, %xmm4
|
|
; SSE-NEXT: andpd %xmm1, %xmm4
|
|
; SSE-NEXT: andnpd %xmm0, %xmm1
|
|
; SSE-NEXT: orpd %xmm4, %xmm1
|
|
; SSE-NEXT: movapd %xmm1, %xmm0
|
|
; SSE-NEXT: retq
|
|
;
|
|
; AVX2-LABEL: PR136368:
|
|
; AVX2: # %bb.0:
|
|
; AVX2-NEXT: vmovddup {{.*#+}} xmm1 = [NaN,NaN]
|
|
; AVX2-NEXT: # xmm1 = mem[0,0]
|
|
; AVX2-NEXT: vandpd %xmm1, %xmm0, %xmm2
|
|
; AVX2-NEXT: vmovsd {{.*#+}} xmm3 = [1.5707963267948966E+0,0.0E+0]
|
|
; AVX2-NEXT: vcmpltsd %xmm2, %xmm3, %xmm2
|
|
; AVX2-NEXT: vandpd %xmm3, %xmm2, %xmm2
|
|
; AVX2-NEXT: vandnpd %xmm0, %xmm1, %xmm0
|
|
; AVX2-NEXT: vandpd %xmm1, %xmm2, %xmm1
|
|
; AVX2-NEXT: vorpd %xmm0, %xmm1, %xmm0
|
|
; AVX2-NEXT: retq
|
|
;
|
|
; AVX512-LABEL: PR136368:
|
|
; AVX512: # %bb.0:
|
|
; AVX512-NEXT: vmovddup {{.*#+}} xmm1 = [NaN,NaN]
|
|
; AVX512-NEXT: # xmm1 = mem[0,0]
|
|
; AVX512-NEXT: vandpd %xmm1, %xmm0, %xmm2
|
|
; AVX512-NEXT: vmovsd {{.*#+}} xmm3 = [1.5707963267948966E+0,0.0E+0]
|
|
; AVX512-NEXT: vcmpltsd %xmm2, %xmm3, %k1
|
|
; AVX512-NEXT: vmovsd %xmm3, %xmm3, %xmm2 {%k1} {z}
|
|
; AVX512-NEXT: vpternlogq {{.*#+}} xmm0 = xmm0 ^ (xmm1 & (xmm0 ^ xmm2))
|
|
; AVX512-NEXT: retq
|
|
%fabs = tail call double @llvm.fabs.f64(double %x)
|
|
%cmp = fcmp ogt double %fabs, 0x3FF921FB54442D18
|
|
%cond = select i1 %cmp, double 0x3FF921FB54442D18, double 0.000000e+00
|
|
%res = tail call double @llvm.copysign.f64(double %cond, double %x)
|
|
ret double %res
|
|
}
|
|
|
|
declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
|
|
declare <4 x float> @llvm.copysign.v4f32(<4 x float> %Mag, <4 x float> %Sgn)
|
|
declare <4 x double> @llvm.copysign.v4f64(<4 x double> %Mag, <4 x double> %Sgn)
|