derek.holloway
7502bf64a4
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27 lines
1.2 KiB
LLVM
27 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=fma | FileCheck %s
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; Propagation of IR FMF should not drop flags when adding the DAG reduction flag.
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; This should include an FMA instruction, not separate FMUL/FADD.
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define double @julia_dotf(<4 x double> %x, <4 x double> %y, <4 x double> %z, i1 %t3) {
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; CHECK-LABEL: julia_dotf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
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; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1
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; CHECK-NEXT: vaddpd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]
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; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%t1 = fmul contract <4 x double> %x, %y
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%t2 = fadd fast <4 x double> %z, %t1
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%rdx.shuf = shufflevector <4 x double> %t2, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
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%bin.rdx22 = fadd fast <4 x double> %t2, %rdx.shuf
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%rdx.shuf23 = shufflevector <4 x double> %bin.rdx22, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%bin.rdx24 = fadd fast <4 x double> %bin.rdx22, %rdx.shuf23
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%t4 = extractelement <4 x double> %bin.rdx24, i32 0
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ret double %t4
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}
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