derek.holloway
7502bf64a4
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35 lines
1.4 KiB
LLVM
35 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Use CPU parameters to ensure that a CPU-specific attribute is not overriding the AVX definition.
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-avx | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx -mattr=-avx | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=btver2 -mattr=-avx | FileCheck %s --check-prefix=SSE
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; No need to load unaligned operand from memory using an explicit instruction with AVX.
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; The operand should be folded into the AND instr.
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; With SSE, folding memory operands into math/logic ops requires 16-byte alignment
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; unless specially configured on some CPUs such as AMD Family 10H.
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define <4 x i32> @test1(ptr %p0, <4 x i32> %in1) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vandps (%rdi), %xmm0, %xmm0
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; CHECK-NEXT: retq
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;
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; SSE-LABEL: test1:
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; SSE: # %bb.0:
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; SSE-NEXT: movups (%rdi), %xmm1
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; SSE-NEXT: andps %xmm1, %xmm0
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; SSE-NEXT: retq
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%in0 = load <4 x i32>, ptr %p0, align 2
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%a = and <4 x i32> %in0, %in1
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ret <4 x i32> %a
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}
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