derek.holloway
7502bf64a4
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230 lines
7.8 KiB
LLVM
230 lines
7.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefixes=SSE,SSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,avx512bw | FileCheck %s --check-prefixes=AVX,AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512
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define <2 x i64> @insert_v2i64_x1(<2 x i64> %a) {
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; SSE2-LABEL: insert_v2i64_x1:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; SSE2-NEXT: retq
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;
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; SSE3-LABEL: insert_v2i64_x1:
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; SSE3: # %bb.0:
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; SSE3-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; SSE3-NEXT: retq
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;
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; SSSE3-LABEL: insert_v2i64_x1:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movlps {{.*#+}} xmm0 = mem[0,1],xmm0[2,3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: insert_v2i64_x1:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: insert_v2i64_x1:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: insert_v2i64_x1:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: insert_v2i64_x1:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX512-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3]
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; AVX512-NEXT: retq
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%1 = insertelement <2 x i64> %a, i64 -1, i32 0
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ret <2 x i64> %1
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}
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define <4 x i64> @insert_v4i64_01x3(<4 x i64> %a) {
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; SSE2-LABEL: insert_v4i64_01x3:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
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; SSE2-NEXT: retq
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;
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; SSE3-LABEL: insert_v4i64_01x3:
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; SSE3: # %bb.0:
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; SSE3-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
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; SSE3-NEXT: retq
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;
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; SSSE3-LABEL: insert_v4i64_01x3:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movlps {{.*#+}} xmm1 = mem[0,1],xmm1[2,3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: insert_v4i64_01x3:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
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; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: insert_v4i64_01x3:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
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; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: insert_v4i64_01x3:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
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; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: insert_v4i64_01x3:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
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; AVX512-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5],ymm0[6,7]
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; AVX512-NEXT: retq
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%1 = insertelement <4 x i64> %a, i64 -1, i32 2
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ret <4 x i64> %1
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}
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define <4 x i32> @insert_v4i32_01x3(<4 x i32> %a) {
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; SSE2-LABEL: insert_v4i32_01x3:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movl $-1, %eax
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; SSE2-NEXT: movd %eax, %xmm1
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; SSE2-NEXT: retq
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;
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; SSE3-LABEL: insert_v4i32_01x3:
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; SSE3: # %bb.0:
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; SSE3-NEXT: movl $-1, %eax
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; SSE3-NEXT: movd %eax, %xmm1
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; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; SSE3-NEXT: retq
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;
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; SSSE3-LABEL: insert_v4i32_01x3:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movl $-1, %eax
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; SSSE3-NEXT: movd %eax, %xmm1
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: insert_v4i32_01x3:
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; SSE41: # %bb.0:
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; SSE41-NEXT: pcmpeqd %xmm1, %xmm1
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; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: insert_v4i32_01x3:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5],xmm0[6,7]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: insert_v4i32_01x3:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: insert_v4i32_01x3:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
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; AVX512-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3]
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; AVX512-NEXT: retq
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%1 = insertelement <4 x i32> %a, i32 -1, i32 2
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ret <4 x i32> %1
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}
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define <8 x i32> @insert_v8i32_x12345x7(<8 x i32> %a) {
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; SSE-LABEL: insert_v8i32_x12345x7:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insert_v8i32_x12345x7:
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; AVX: # %bb.0:
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; AVX-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = insertelement <8 x i32> %a, i32 -1, i32 0
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%2 = insertelement <8 x i32> %1, i32 -1, i32 6
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ret <8 x i32> %2
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}
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define <8 x i16> @insert_v8i16_x12345x7(<8 x i16> %a) {
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; SSE-LABEL: insert_v8i16_x12345x7:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insert_v8i16_x12345x7:
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; AVX: # %bb.0:
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; AVX-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = insertelement <8 x i16> %a, i16 -1, i32 0
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%2 = insertelement <8 x i16> %1, i16 -1, i32 6
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ret <8 x i16> %2
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}
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define <16 x i16> @insert_v16i16_x12345x789ABCDEx(<16 x i16> %a) {
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; SSE-LABEL: insert_v16i16_x12345x789ABCDEx:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insert_v16i16_x12345x789ABCDEx:
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; AVX: # %bb.0:
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; AVX-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = insertelement <16 x i16> %a, i16 -1, i32 0
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%2 = insertelement <16 x i16> %1, i16 -1, i32 6
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%3 = insertelement <16 x i16> %2, i16 -1, i32 15
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ret <16 x i16> %3
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}
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define <16 x i8> @insert_v16i8_x123456789ABCDEx(<16 x i8> %a) {
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; SSE-LABEL: insert_v16i8_x123456789ABCDEx:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insert_v16i8_x123456789ABCDEx:
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; AVX: # %bb.0:
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; AVX-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = insertelement <16 x i8> %a, i8 -1, i32 0
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%2 = insertelement <16 x i8> %1, i8 -1, i32 15
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ret <16 x i8> %2
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}
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define <32 x i8> @insert_v32i8_x123456789ABCDEzGHIJKLMNOPQRSTxx(<32 x i8> %a) {
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; SSE-LABEL: insert_v32i8_x123456789ABCDEzGHIJKLMNOPQRSTxx:
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; SSE: # %bb.0:
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
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; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: insert_v32i8_x123456789ABCDEzGHIJKLMNOPQRSTxx:
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; AVX: # %bb.0:
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; AVX-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
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; AVX-NEXT: retq
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%1 = insertelement <32 x i8> %a, i8 -1, i32 0
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%2 = insertelement <32 x i8> %1, i8 -1, i32 15
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%3 = insertelement <32 x i8> %2, i8 -1, i32 30
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%4 = insertelement <32 x i8> %3, i8 -1, i32 31
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ret <32 x i8> %4
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}
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