derek.holloway
7502bf64a4
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48 lines
1.2 KiB
LLVM
48 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefixes=CHECK,X64
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; It doesn't matter if an x86-64 target has specified "no-sse2"; we still can use mfence.
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define void @test() {
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; X86-LABEL: test:
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; X86: # %bb.0:
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; X86-NEXT: mfence
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; X86-NEXT: retl
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;
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; X64-LABEL: test:
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; X64: # %bb.0:
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; X64-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: retq
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fence seq_cst
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ret void
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}
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define i32 @fence(ptr %ptr) {
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; X86-LABEL: fence:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: mfence
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; X86-NEXT: movl (%eax), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: fence:
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; X64: # %bb.0:
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; X64-NEXT: lock orl $0, -{{[0-9]+}}(%rsp)
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: retq
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%atomic = atomicrmw add ptr %ptr, i32 0 seq_cst
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ret i32 %atomic
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}
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define void @mfence() nounwind {
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; CHECK-LABEL: mfence:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mfence
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; CHECK-NEXT: ret{{[l|q]}}
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call void @llvm.x86.sse2.mfence()
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ret void
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}
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declare void @llvm.x86.sse2.mfence() nounwind readnone
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