derek.holloway
7502bf64a4
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303 lines
10 KiB
LLVM
303 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
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; If we are transferring XMM conversion results to MMX registers we could use the MMX equivalents
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; (CVTPD2PI/CVTTPD2PI + CVTPS2PI/CVTTPS2PI) without affecting rounding/exceptions etc.
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define void @cvt_v2f64_v2i32(<2 x double>, ptr) nounwind {
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; X86-LABEL: cvt_v2f64_v2i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cvtpd2pi %xmm0, %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: cvt_v2f64_v2i32:
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; X64: # %bb.0:
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; X64-NEXT: cvtpd2pi %xmm0, %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq %mm0, (%rdi)
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; X64-NEXT: retq
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%3 = tail call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %0)
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%4 = bitcast <4 x i32> %3 to <2 x i64>
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%5 = extractelement <2 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <1 x i64>
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%7 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %6, <1 x i64> %6)
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%8 = bitcast <1 x i64> %7 to i64
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%9 = insertelement <1 x i64> undef, i64 %8, i32 0
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store <1 x i64> %9, ptr %1
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ret void
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}
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define void @cvtt_v2f64_v2i32(<2 x double>, ptr) nounwind {
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; X86-LABEL: cvtt_v2f64_v2i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cvttpd2pi %xmm0, %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: cvtt_v2f64_v2i32:
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; X64: # %bb.0:
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; X64-NEXT: cvttpd2pi %xmm0, %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq %mm0, (%rdi)
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; X64-NEXT: retq
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%3 = tail call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %0)
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%4 = bitcast <4 x i32> %3 to <2 x i64>
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%5 = extractelement <2 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <1 x i64>
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%7 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %6, <1 x i64> %6)
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%8 = bitcast <1 x i64> %7 to i64
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%9 = insertelement <1 x i64> undef, i64 %8, i32 0
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store <1 x i64> %9, ptr %1
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ret void
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}
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define void @fptosi_v2f64_v2i32(<2 x double>, ptr) nounwind {
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; X86-LABEL: fptosi_v2f64_v2i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cvttpd2pi %xmm0, %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: fptosi_v2f64_v2i32:
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; X64: # %bb.0:
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; X64-NEXT: cvttpd2pi %xmm0, %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq %mm0, (%rdi)
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; X64-NEXT: retq
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%3 = fptosi <2 x double> %0 to <2 x i32>
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%4 = bitcast <2 x i32> %3 to <1 x i64>
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%5 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %4, <1 x i64> %4)
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%6 = bitcast <1 x i64> %5 to i64
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%7 = insertelement <1 x i64> undef, i64 %6, i32 0
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store <1 x i64> %7, ptr %1
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ret void
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}
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define void @cvt_v2f32_v2i32(<4 x float>, ptr) nounwind {
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; X86-LABEL: cvt_v2f32_v2i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cvtps2pi %xmm0, %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: cvt_v2f32_v2i32:
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; X64: # %bb.0:
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; X64-NEXT: cvtps2pi %xmm0, %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq %mm0, (%rdi)
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; X64-NEXT: retq
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%3 = tail call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %0)
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%4 = bitcast <4 x i32> %3 to <2 x i64>
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%5 = extractelement <2 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <1 x i64>
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%7 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %6, <1 x i64> %6)
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%8 = bitcast <1 x i64> %7 to i64
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%9 = insertelement <1 x i64> undef, i64 %8, i32 0
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store <1 x i64> %9, ptr %1
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ret void
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}
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define void @cvtt_v2f32_v2i32(<4 x float>, ptr) nounwind {
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; X86-LABEL: cvtt_v2f32_v2i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cvttps2pi %xmm0, %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: cvtt_v2f32_v2i32:
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; X64: # %bb.0:
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; X64-NEXT: cvttps2pi %xmm0, %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq %mm0, (%rdi)
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; X64-NEXT: retq
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%3 = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %0)
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%4 = bitcast <4 x i32> %3 to <2 x i64>
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%5 = extractelement <2 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <1 x i64>
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%7 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %6, <1 x i64> %6)
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%8 = bitcast <1 x i64> %7 to i64
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%9 = insertelement <1 x i64> undef, i64 %8, i32 0
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store <1 x i64> %9, ptr %1
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ret void
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}
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define void @fptosi_v4f32_v4i32(<4 x float>, ptr) nounwind {
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; X86-LABEL: fptosi_v4f32_v4i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cvttps2pi %xmm0, %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: fptosi_v4f32_v4i32:
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; X64: # %bb.0:
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; X64-NEXT: cvttps2pi %xmm0, %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq %mm0, (%rdi)
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; X64-NEXT: retq
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%3 = fptosi <4 x float> %0 to <4 x i32>
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%4 = shufflevector <4 x i32> %3, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%5 = bitcast <2 x i32> %4 to <1 x i64>
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%6 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %5, <1 x i64> %5)
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%7 = bitcast <1 x i64> %6 to i64
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%8 = insertelement <1 x i64> undef, i64 %7, i32 0
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store <1 x i64> %8, ptr %1
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ret void
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}
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define void @fptosi_v2f32_v2i32(<4 x float>, ptr) nounwind {
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; X86-LABEL: fptosi_v2f32_v2i32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: cvttps2pi %xmm0, %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: fptosi_v2f32_v2i32:
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; X64: # %bb.0:
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; X64-NEXT: cvttps2pi %xmm0, %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq %mm0, (%rdi)
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; X64-NEXT: retq
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%3 = fptosi <4 x float> %0 to <4 x i32>
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%4 = bitcast <4 x i32> %3 to <2 x i64>
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%5 = extractelement <2 x i64> %4, i32 0
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%6 = bitcast i64 %5 to <1 x i64>
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%7 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %6, <1 x i64> %6)
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%8 = bitcast <1 x i64> %7 to i64
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%9 = insertelement <1 x i64> undef, i64 %8, i32 0
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store <1 x i64> %9, ptr %1
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ret void
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}
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; FIXME: If we are transferring MMX registers to XMM for conversion we could use the MMX equivalents
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; (CVTPI2PD + CVTPI2PS) without affecting rounding/exceptions etc.
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define <2 x double> @sitofp_v2i32_v2f64(ptr) nounwind {
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; X86-LABEL: sitofp_v2i32_v2f64:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: movl 8(%ebp), %eax
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; X86-NEXT: movq (%eax), %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%esp)
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; X86-NEXT: cvtdq2pd (%esp), %xmm0
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: sitofp_v2i32_v2f64:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq2dq %mm0, %xmm0
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; X64-NEXT: cvtdq2pd %xmm0, %xmm0
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; X64-NEXT: retq
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%2 = load <1 x i64>, ptr %0, align 8
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%3 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %2, <1 x i64> %2)
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%4 = bitcast <1 x i64> %3 to i64
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%5 = insertelement <2 x i64> undef, i64 %4, i32 0
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%6 = bitcast <2 x i64> %5 to <4 x i32>
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%7 = shufflevector <4 x i32> %6, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%8 = sitofp <2 x i32> %7 to <2 x double>
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ret <2 x double> %8
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}
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define <4 x float> @sitofp_v2i32_v2f32(ptr) nounwind {
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; X86-LABEL: sitofp_v2i32_v2f32:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movq (%eax), %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq2dq %mm0, %xmm0
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; X86-NEXT: cvtdq2ps %xmm0, %xmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: sitofp_v2i32_v2f32:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq2dq %mm0, %xmm0
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; X64-NEXT: cvtdq2ps %xmm0, %xmm0
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; X64-NEXT: retq
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%2 = load <1 x i64>, ptr %0, align 8
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%3 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %2, <1 x i64> %2)
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%4 = bitcast <1 x i64> %3 to <2 x i32>
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%5 = shufflevector <2 x i32> %4, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%6 = sitofp <4 x i32> %5 to <4 x float>
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ret <4 x float> %6
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}
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define <4 x float> @cvt_v2i32_v2f32(ptr) nounwind {
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; X86-LABEL: cvt_v2i32_v2f32:
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; X86: # %bb.0:
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; X86-NEXT: pushl %ebp
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; X86-NEXT: movl %esp, %ebp
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; X86-NEXT: andl $-8, %esp
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: movl 8(%ebp), %eax
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; X86-NEXT: movq (%eax), %mm0
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; X86-NEXT: paddd %mm0, %mm0
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; X86-NEXT: movq %mm0, (%esp)
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; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-NEXT: cvtdq2ps %xmm0, %xmm0
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; X86-NEXT: movl %ebp, %esp
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; X86-NEXT: popl %ebp
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; X86-NEXT: retl
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;
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; X64-LABEL: cvt_v2i32_v2f32:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %mm0
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; X64-NEXT: paddd %mm0, %mm0
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; X64-NEXT: movq2dq %mm0, %xmm0
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; X64-NEXT: cvtdq2ps %xmm0, %xmm0
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; X64-NEXT: retq
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%2 = load <1 x i64>, ptr %0, align 8
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%3 = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %2, <1 x i64> %2)
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%4 = bitcast <1 x i64> %3 to i64
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%5 = insertelement <2 x i64> undef, i64 %4, i32 0
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%6 = insertelement <2 x i64> %5, i64 0, i32 1
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%7 = bitcast <2 x i64> %6 to <4 x i32>
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%8 = tail call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %7)
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ret <4 x float> %8
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}
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define noundef <2 x i64> @cvt_f64_v2i64(double %a0) {
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; X86-LABEL: cvt_f64_v2i64:
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; X86: # %bb.0:
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; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X86-NEXT: retl
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;
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; X64-LABEL: cvt_f64_v2i64:
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; X64: # %bb.0:
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; X64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
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; X64-NEXT: retq
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%bc = bitcast double %a0 to <1 x i64>
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%r = shufflevector <1 x i64> %bc, <1 x i64> zeroinitializer, <2 x i32> <i32 0, i32 1>
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ret <2 x i64> %r
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}
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declare <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64>, <1 x i64>)
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declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>)
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declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>)
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declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>)
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declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>)
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declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>)
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